adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 54

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

ASRC Output Rate Select Pairs[7:0] Registers (Address 0xE088 to Address 0xE08F)
Table 32. Bit Descriptions of ASRC Output Rate Select Pairs[7:0] Registers
Bit Position
[15:6]
[5:0]
ASRC Output Rate Bits (Bits[5:0])
These bits select the output conversion rate for the eight ASRCs.
Any asynchronous input to the ASRC is output at this rate. It
can be set by one of the 12 serial output channel pairs’ f
signals (the LRCLK associated with their automatically assigned
serial port) or by the core’s f
In the case of the ADAU1442, each of the eight stereo ASRCs
can have separate output rates.
In the case of the ADAU1445, each stereo output from the
ASRCs can have a separate data output; however, all outputs
from ASRCs[3:0] must be synchronous to each other, and all
Description
Reserved
ASRC output rate
000000 = Serial Output Pair 0 (Channel 0, Channel 1)
000001 = Serial Output Pair 1 (Channel 2, Channel 3)
000010 = Serial Output Pair 2 (Channel 4, Channel 5)
000011 = Serial Output Pair 3 (Channel 6, Channel 7)
000100 = Serial Output Pair 4 (Channel 8, Channel 9)
000101 = Serial Output Pair 5 (Channel 10, Channel 11)
000110 = Serial Output Pair 6 (Channel 12, Channel 13)
000111 = Serial Output Pair 7 (Channel 14, Channel 15)
001000 = Serial Output Pair 8 (Channel 16, Channel 17)
001001 = Serial Output Pair 9 (Channel 18, Channel 19)
001010 = Serial Output Pair 10 (Channel 20, Channel 21)
001011 = Serial Output Pair 11 (Channel 22, Channel 23)
010000 = DSP rate
010001 = internal f
010010 = internal f
010011 = internal f
111111 = no rate
S,NORMAL
, f
S,DUAL
, or f
S,NORMAL
S,DUAL
S,QUAD
S,QUAD
rate
rate
clock signals.
rate
S
clock
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outputs from ASRCs[7:4] must be synchronous to each other.
The first group of ASRCs (ASRCs[3:0]) takes its output rate
from the setting on the ASRC 0 output. The output rate for
ASRCs[3:1] are automatically set to this rate, ignoring the
settings for the ASCRs[3:1] outputs. The second group of
ASRCs (ASRCs[7:4]) takes its output rate from the setting on
the ASRC 4 output. The output rate for ASRCs[7:5] are
automatically set to this rate, ignoring the settings for the
ASRCs[7:5] outputs.
In the case of the ADAU1446, which contains no ASRCs, these
registers do not affect system operation in any way and can be
ignored.
Default
111111