adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 19

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

MASTER CLOCK AND PLL
Using the Oscillator
The ADAU144x can use an on-board oscillator to generate its
master clock. However, an external crystal must be attached to
complete the oscillator circuit. The on-board oscillator is designed
to work with a 256 × f
when f
44.1 kHz. The resonant frequency of this crystal should be in this
range even in the case when the core is processing double- or
quad-rate signals. When the core is processing dual-rate signals
(for example, f
the the crystal should be 128 × f
quad-rate signals (for example, f
frequency of the crystal should be 64 × f
The external crystal in the circuit should be an AT-cut parallel
resonance device operating at its fundamental frequency.
Ceramic resonators should not be used. Figure 9 shows the
crystal oscillator circuit recommended for proper operation.
For systems operating in very cold environments, the equivalent
series resistance (ESR) of the crystal can increase, potentially
leading to start-up issues. In this situation, the ESR can be
decreased by placing a 1 MΩ resistor between the XTALO and
XTALI pins.
The 100 Ω damping resistor on XTALO provides the oscillator
with a voltage swing of approximately 2.2 V at the XTALI pin.
The crystal shunt capacitance should be 7 pF. Its optimal load
capacitance, specified by the manufacturer, should be about 18 pF,
although the circuit supports values up to 25 pF. The equivalent
series resistance should also be as small as possible. The necessary
values of Load Capacitor C1 and Load Capacitor C2 can be
calculated from the crystal load capacitance with the following
equation:
where C
assumed to be approximately 2 pF to 5 pF.
Short trace lengths in the oscillator circuit decrease stray
capacitance, thereby increasing the loop gain of the circuit and
helping to avoid crystal start-up problems.
On the ADAU144x evaluation boards, the capacitance value for
C1 and C2 is 22 pF.
C =
S,NORMAL
L
STRAY
C
C
1
1
is the stray capacitance in the circuit and is usually
S,DUAL
×C
+ C
is 48 kHz and 11.2896 MHz when f
2
2
Figure 9. Crystal Oscillator Circuit
= 88.2 kHz or 96 kHz), resonant frequency of
+ C
S,NORMAL
C1
C2
STRAY
master clock, which is 12.288 MHz
100Ω
S,DUAL
S,QUAD
; when the core is processing
XTALO
XTALI
= 192 kHz), the resonant
S,QUAD
.
S,NORMAL
is
Rev. PrA| Page 19 of 92
XTALO should not be used to directly drive the crystal signal to
another IC. This signal is an analog sine wave and is not
appropriate to drive a digital input. A separate pin, CLKOUT, is
provided for this purpose. CLKOUT can output 256 × f
512 × f
oscillator signal to other ICs in the system. CLKOUT is set up
using the CLKMODEx pins. For a more detailed explanation of
CLKOUT, refer to the Using the ADAU144x as a Clock Master
section.
Setting Master Clock and PLL Mode
The ADAU144x master clock input feeds a PLL, which generates
the 3584 × f
to run the DSP core. This rate is referred to as f
operation, the input to the master clock must be one of the
following: 64 × f
384 × f
sampling rate with the core in normal-rate processing mode.
The PLL divider mode is set by PLL0, PLL1, and PLL2 as
detailed in Table 7.
If the ADAU144x core is set to receive double-rate signals (by
reducing the number of program steps per sample by a factor of 2
using the DSP core rate select register), then the master clock
frequency must be 32 × f
or 256 × f
If the ADAU144x core is set to receive quad-rate signals (by
reducing the number of program steps per sample by a factor of 4
using the DSP core rate select register), then the master clock
frequency must be 16 × f
or 128 × f
XTALI so that the ADAU144x can complete its initialization
routine.
If, at any point during operation, the clock signal is removed
from XTALI, the DSP should be reset to avoid unpredictable
behavior on output pins. The clock mode should not be changed
without also resetting the ADAU144x. If the mode is changed
during operation, a click or pop can result on the outputs. The
state of the PLLx pins should be changed while RESET is held low.
The phase-locked loop uses the PLL mode select pins (PLL0,
PLL1, and PLL2) to derive a 64 × f
signal is present at the XTALI pin. This clock signal is multiplied
by 56 to produce the core clock. Therefore, f
In a system with a f
clock and then multiplies it by 56 to produce a 172.032 MHz
core clock.
The core clock (f
though it may be lower in some applications.
S,NORMAL
S,NORMAL
S,QUAD
S,DUAL
S,NORMAL
, or a buffered, digital copy of the crystal
, or 512 × f
. On power-up, a clock signal must be present on
.
S,NORMAL
CORE
S,NORMAL
clock (172.032 MHz when f
) should never exceed 172.032 MHz,
, 128 × f
S,DUAL
S,QUAD
S,NORMAL
of 48 kHz, the PLL derives a 3.072 MHz
, 64 × f
, 32 × f
S,NORMAL
, where f
S,NORMAL
S,DUAL
S,QUAD
, 256 × f
, 128 × f
, 64 × f
S,NORMAL
clock from whatever
CORE
S,NORMAL
is 3584 × f
S,DUAL
S,NORMAL
S,QUAD
CORE
is the audio
. In normal
, 192 × f
, 96 × f
is 48 kHz)
,
S,NORMAL
S,NORMAL
S,QUAD
S,DUAL
.
,
,
,