adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 86

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

LAYOUT RECOMMENDATIONS
Parts Placement
All 100 nF bypass capacitors, which are recommended for every
analog, digital, and PLL power-ground pair, should be placed as
close to the ADAU144x as possible. The AVDD, DVDD, PVDD,
and IOVDD supply signals on the board should each be bypassed
with an additional single bulk capacitor (10 μF to 47 μF).
All traces in the crystal oscillator circuit (Figure 9) should be
kept as short as possible to minimize stray capacitance. There
should not be any long board traces connected to crystal
oscillator circuit components because such traces may affect
crystal startup and operation.
Grounding
A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.
Exposed Pad PCB Design
The ADAU1442 and ADAU1445 packages include an exposed pad
for improved heat disippation. When designing a board for such
a package, special consideration should be given to the following:
•
•
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
Figure 60).
Vias should be placed to connect all layers of copper, allowing
for efficient heat and energy conductivity. For an example,
see Figure 61, which has 16 vias arranged in a 4 × 4 grid in
the pad area.
Figure 60. Exposed Pad Layout Example—Side View
VIAS
COPPER SQUARES
TOP
GROUND
POWER
BOTTOM
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PLL Loop Filter
The single resistor and two capacitors in the PLL loop filter
should be connected to the PLL_FILT and PVDD pins with
short traces to minimize jitter.
Power Supply Bypass Capacitors
Each power supply pin should be bypassed to its nearest
appropriate ground pin with a single 100 nF capacitor. The
connections to each side of the capacitor should be as short as
possible, and the trace should stay on a single layer with no vias.
For maximum effectiveness, the capacitor should preferably be
located either equidistant from the power and ground pins or,
when equidistant placement is not possible, slightly closer to the
power pin. Thermal connections to the planes should be made
on the far side of the capacitor.
EOS/ESD Protection
Although the ADAU144x has robust internal protection
circuitry against overvoltages and electrostatic discharge, an
external transient voltage suppressor (TVS) is recommended for
all systems to prevent damage to the IC. Examples can be found
in the AN-311 Application Note on the Analog Devices website.
Figure 62. Recommended Power Supply Bypass Capacitor Layout
Figure 61. Exposed Pad Layout Example—Top View
CAPACITOR
TO VDD
VDD
TO GND
GND