adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 27

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

SPI Port
By default, the ADAU144x is in I
SPI control mode by pulling CLATCH low three times. The SPI
port uses a 4-wire interface, consisting of CLATCH, CCLK,
CDATA, and COUT signals. The CLATCH signal goes low at
the beginning of a transaction and high at the end of a transaction.
The CCLK signal latches CDATA on a low-to-high transition.
COUT data is shifted out of the ADAU144x on the falling edge
of CCLK and should be clocked into a receiving device, such as
a microcontroller, on the CCLK rising edge. The CDATA signal
carries the serial input data, and the COUT signal is the serial
output data. The COUT signal remains three-stated until a read
operation is requested. This allows other SPI-compatible periph­
erals to share the same readback line. All SPI transactions have
the same word sequence shown in Table 13 (see Figure 4 for a
SPI port timing diagram). All data written should be MSB first.
Chip Address R/ W
The first byte of an SPI transaction includes the 7-bit chip address
and a R/ W bit. The chip address is set by the ADDR0 pin. This
allows two ADAU144x devices to share a CLATCH signal, yet
still operate independently. When ADDR0 is low, the chip address
is 0000000; when ADDR0 is high, the address is 0000001. The
Table 13. Generic Control Word Sequence
Byte 0
Chip Address[6:0], R/W
1
Continues to end of data.
CLATCH
CDATA
CCLK
CLATCH
CDATA
COUT
CCLK
2
BYTE 0
C mode, but it can be put into
Byte 1
Subaddress[15:8]
HIGH-Z
BYTE 0
Figure 19. SPI Write Clocking (Single-Write Mode)
Figure 20. SPI Read Clocking (Single-Read Mode)
BYTE 1
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DATA
Byte 2
Subaddress[7:0]
LSB of the first byte determines whether the SPI transaction is a
read (Logic Level 1) or a write (Logic Level 0). Users can com­
municate with both ICs with up to five latch signals by using the
USBi communication channel list in the hardware configuration
tab in SigmaStudio.
Subaddress
The 16-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. In burst write mode, an initial
subaddress is given followed by a continuous sequence of data
for consecutive memory or register locations. The detailed data
format for continuous mode operation is shown in Figure 4.
A sample timing diagram for a single SPI write operation to the
parameter RAM is shown in Figure 19. A sample timing
diagram of a single SPI read operation is shown in Figure 20.
The COUT pin goes from three-state to driven at the beginning
of Byte 3. In this example, Byte 0 to Byte 2 contain the addresses
and R/ W bit, and subsequent bytes carry the data.
BYTE 1
DATA
BYTE 2
Byte 3
Data
DATA
BYTE 3
HIGH-Z
Byte 4
Data
1