adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 42

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

Table 28. Bit Descriptions of Serial Output Port Modes Registers
Bit Position
[15]
[14]
[13:10]
[9]
[8]
[7:6]
[5:3]
[2:0]
1
2
3
Bit 15 and Bits[13:10] must be used in conjunction to set the port as a master or slave.
The default depends on the address: 0x040 = 0000, 0xE041 = 0001, 0xE042 = 0010, 0xE043 = 0011, 0xE044 = 0100, 0xE045 = 0101, 0xE046 = 0110, 0xE047 = 0111,
0xE048 = 1000, and 0xE049 = 1001.
To activate flexible TDM mode, both Bits[7:6] and Bits[2:0] must be set.
Description
Clock output enable
0 = LRCLK and BCLK output pins disabled
1 = LRCLK and BCLK output pins enabled
Frame sync type
0 = LRCLK 50/50 duty cycle clock signal (square wave)
1 = LRCLK synchronization pulse (narrow pulse)
Clock domain master/slave select
0000 = slave to Clock Domain 3 (Port 1)
0001 = slave to Clock Domain 4 (Port 2)
0010 = slave to Clock Domain 5 (Port 3)
0011 = slave to Clock Domain 6 (Port 4)
0100 = slave to Clock Domain 7 (Port 5)
0101 = slave to Clock Domain 8 (Port 6)
0110 = slave to Clock Domain 9 (Port 7)
0111 = slave to Clock Domain 10 (Port 8)
1000 = slave to Clock Domain 11 (Port 9)
1001 = master, clock is f
1010 = master, clock is f
1011 = master, clock is f
Serial output BCLK polarity
0 = negative BCLK polarity
1 = positive BCLK polarity
Serial output LRCLK polarity
0 = negative BCLK polarity
1 = positive BCLK polarity
Word length
00 = 24 bits
01 = 20 bits
10 = 16 bits
11 = flexible TDM mode
MSB position
000 = I
001 = left justified (delayed by 0)
010 = delayed by 8
011 = delayed by 12
100 = delayed by 16
TDM type
000 = TDM2 (stereo)
001 = TDM4
010 = TDM8 or flexible TDM mode
011 = TDM16
100 = packed TDM4
2
S (delayed by 1)
1
S,NORMAL
S,DUAL
S,QUAD
3
1
3
Rev. PrA | Page 42 of 92
Default
0
0
Address specific
0
0
00
000
000
2