adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 25

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

data. A Logic 0 on the LSB of the first byte means the master
writes information to the peripheral. A Logic 1 on the LSB of
the first byte means the master reads information from the
peripheral. A data transfer takes place until a stop condition is
encountered. A stop condition occurs when SDA transitions
from low to high while SCL is held high. Figure 13 shows the
timing of an I
Burst mode addressing, where the subaddresses are automatically
incremented at word boundaries, can be used for writing large
amounts of data to contiguous memory locations. This increment
happens automatically, unless a stop condition is encountered after
a single-word write. The registers and RAMs in the ADAU144x
range in width from one to five bytes, so the auto-increment feature
knows the mapping between subaddresses and the word length
of the destination register (or memory location). A data transfer
is always terminated by a stop condition.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCL high period, the user
should only issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADAU144x does
not issue an acknowledge and returns to the idle condition. If
the user exceeds the highest subaddress while in auto-increment
mode, one of two actions is taken. In read mode, the ADAU144x
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no-acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. If the highest subaddress
location is reached while in write mode, the data for the invalid
byte is not loaded into any subaddress register, a no acknowledge is
issued by the ADAU144x, and the part returns to the idle condition.
(CONTINUED)
(CONTINUED)
START BY
MASTER
SCL
SDA
SCL
SDA
2
C write.
0
1
1
CHI P ADDRESS BYTE
SUBADDRESS BYTE 2
1
FRAME 1
FRAME 2
0
0
ADR
SEL
Figure 13. I
Rev. PrA| Page 25 of 92
R/W
ADAU144x
ADAU144x
ACK BY
ACK BY
2
C Write Clocking
I
Figure 15 shows the sequence of a single-word write operation.
Every ninth clock, the ADAU144x issues an acknowledge by
pulling SDA low.
Figure 16 shows the sequence of a burst mode write operation.
This figure shows an example where the target destination registers
are two bytes. The ADAU144x knows to increment its subaddress
register every two bytes because the requested subaddress cor­
responds to a register or memory area with a 2-byte word length.
The sequence of a single-word read operation is shown in
Figure 17. Note that, even though this is a read operation, the
first R/ W bit is a 0, indicating a write operation. This is because
the subaddress needs to be written to set up the internal
address. After the ADAU144x acknowledges the receipt of the
subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/ W set to 1,
indicating a read operation. This causes the ADAU144x SDA
pin to switch directions and begin driving data back to the
master. The master then responds every ninth pulse with an
acknowledge pulse to the ADAU144x.
Figure 18 shows the sequence of a burst mode read operation.
This figure shows an example where the target read registers are
two bytes. The ADAU144x increments its subaddress every two
bytes because the requested subaddress corresponds to a
register or memory area with word lengths of two bytes. Other
address ranges can have a variety of word lengths, ranging from
one to five bytes; the ADAU144x always decodes the subaddress
and sets the auto-increment circuit so that the address
increments after the appropriate number of bytes.
2
C Read and Write Operations
SUBADDRESS BYTE 1
DATA BYTE 1
FRAME 3
FRAME 2
ADAU144x
ADAU144x
ACK BY
ACK BY
STOP BY
MASTER