adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 6

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

DIGITAL TIMING SPECIFICATIONS
Table 2.
Parameter
MASTER CLOCK
SERIAL PORT
SPI PORT
I
MULTIPURPOSE PINS AND RESET
1
2
All timing specifications are given for the default (I
C PORT
t
f
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MP
BCLK
BIL
BIH
LIS
LIH
SIS
SIH
TS
SODS
SODM
CCLK
CCPL
CCPH
CLS
CLH
CLPH
CDS
CDH
COD
SCL
SCLH
SCLL
SCS
SCH
DS
SCR
SCF
SDR
SDF
BFT
GRT
GFT
GIL
RLPW
1
t
TBD
TBD
40, TBD
40, TBD
10, TBD
10, TBD
10, TBD
10, TBD
80, TBD
80, TBD
0, TBD
100, TBD
80, TBD
0, TBD
80, TBD
TBD
0.6, TBD
1.3, TBD
0.6, TBD
0.6, TBD
100, TBD
0.6, TBD
20, TBD
MIN
2
S) states of the serial audio input ports and the serial audio output ports (see Table 24 and Table 28).
t
TBD
24.576
5
40, TBD
40, TBD
25, TBD
101, TBD
400
300, TBD
300, TBD
300, TBD
300, TBD
50, TBD
50, TBD
1.5 ×
1/f,
MAX
S,NORMAL
TBD
Rev. PrA | Page 6 of 92
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
μs
ns
Description
Master clock (MCLK) period.
BCLK frequency.
BCLKx low pulse width.
BCLKx high pulse width.
LRCLKx setup to BCLKx input rising edge.
LRCLKx hold from BCLKx input rising edge.
SDATA_INx setup to BCLKx input rising edge.
SDATA_INx hold from BCLKx input rising edge.
BCLKx output falling edge to LRCLKx output timing skew.
SDATA_OUTx delay in slave mode from BCLKx output falling edge.
SDATA_OUTx delay in master mode from BCLKx output falling edge.
CCLK frequency.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup to CCLK rising edge.
CLATCH hold from CCLK rising edge.
CLATCH pulse width high.
CDATA setup to CCLK rising edge.
CDATA hold from CCLK rising edge.
COUT delay from CCLK falling edge.
SCL clock frequency.
SCL high.
SCL low.
Setup time. Relevant for repeated start condition.
Hold time. After this period, the first clock is generated.
Data setup time.
SCL rise time.
SCL fall time.
SDA rise time.
SDA fall time.
Bus-free time between stop and start.
MPx pin rise time.
MPx pin fall time.
MPx pin input latency until high/low value is read by core. Guaranteed
by design.
RESET low pulse width.