adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 66

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

Auxiliary Outputs—Set Enable Mode Register
(Address 0xE0C8)
Table 56. Bit Descriptions of Register 0xE0C8
Bit
Position
[15:2]
[1:0]
This register controls when the S/PDIF stream is active on the
multipurpose pins when the S/PDIF to I
more information, see the Enable S/PDIF to I
Setting Bits[1:0] of Register 0xE0C8 to 10 (auxiliary outputs are
off on reset) is useful for situations where the S/PDIF stream
may be interrupted unexpectedly. An interruption causes the
S/PDIF lock bit to go low, which in turn disables the auxiliary
outputs. When the S/PDIF stream is recovered, the hot enable
bit must be activated to restore the auxiliary outputs (see the Set
Hot Enable Register (Address 0xE0CA) section for more
information).
S/PDIF Lock Bit Detection Register (Address 0xE0C9)
Table 57. Bit Descriptions of Register 0xE0C9
Bit
Position
[15:1]
[0]
This read-only register shows the status of the S/PDIF input
lock bit.
Set Hot Enable Register (Address 0xE0CA)
Table 58. Bit Descriptions of Register 0xE0CA
Bit
Position
[15:1]
[0]
Description
Reserved
Word length
00 = auxiliary outputs are always off.
01 = auxiliary outputs are always on.
10 = auxiliary outputs are off on reset.
(They switch on as soon as the hot enable
bit is 1 and switch off as soon as the S/PDIF
lock bit is 0.)
Description
Reserved
S/PDIF input lock bit (read only)
0 = no valid input stream
1 = successful lock to input stream
Description
Reserved
Hot enable bit
0 = hot enable inactive
1 = hot enable active
2
S mode is active. For
2
S Output section.
Default
01
Default
0
Rev. PrA | Page 66 of 92
This register allows the hot enable bit to be set, which restarts the
auxiliary outputs when they are configured so that the auxiliary
outputs are off on a reset (that is, Bits[1:0] of Register 0xE0C8 are
set to 10). The hot enable bit is set to 0 automatically in the event
that the S/PDIF receiver loses lock. For more information, see the
Auxiliary Outputs—Set Enable Mode Register (Address 0xE0C8)
section.
Read Enable Auxiliary Output Register (Address 0xE0CB)
Table 59. Bit Descriptions of Register 0xE0CB
Bit
Position
[15:1]
[0]
This read-only register shows the status of the S/PDIF auxiliary
outputs.
S/PDIF Loss-of-Lock Behavior Register (Address 0xE0CC)
Table 60. Bit Descriptions of Register 0xE0CC
Bit
Position
[15:1]
[0]
This register controls the behavior of the S/PDIF receiver in the
event of a loss of lock to the input stream. A loss of lock can
arise when there is severe noise or jitter on the S/PDIF input
stream, rendering it unrecognizable to the receiver. In the
default mode, such an event disables the S/PDIF receiver,
causing it to stop outputting frame sync pulses. This in turn
causes the target ASRC to be muted. Frame sync pulses do not
resume until lock is regained.
When the register is set to 1, the S/PDIF receiver always outputs
frame sync pulses, even if the integrity of the S/PDIF stream is
compromised and the audio samples cannot be recovered. In
such a case, the S/PDIF receiver data output remains at 0 until
lock is regained.
The S/PDIF receiver is robust and can recover streams with
integrity well below the standards of the AES/EBU
specification. Therefore, even in cases of extreme signal
degradation, this register should be used only when audio
recovery is required. In general, a loss-of-lock event is much
shorter than an ASRC mute or unmute ramp.
Description
Reserved
S/PDIF loss-of-lock behavior
0 = S/PDIF disable on loss of lock
1 = S/PDIF ignore loss of lock
Description
Reserved
Read enable auxiliary output (read only)
0 = S/PDIF auxiliary outputs disabled
1 = S/PDIF auxiliary outputs enabled
Default
0