adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 12

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

Pin No.
30
31
32
33
34
35
36
40
41
42
43
44
45
46
47
48
49
53
54
55
56
57
58
59
60
61
Mnemonic
CLKMODE0
RSVD
PLL2
MP7
MP6
MP5
MP4
VDRIVE
XTALO
XTALI
PLL_FILT
PVDD
PGND
SPDIFI
SPDIFO
AVDD
AGND
CLKOUT
RESET
MP3/ADC3
MP2/ADC2
MP1/ADC1
MP0/ADC0
PLL1
PLL0
SDATA_OUT8
Type
D_IN
D_IN
D_IN
D_IO
D_IO
D_IO
D_IO
A_OUT
A_OUT
A_IN
A_OUT
PWR
PWR
D_IN
D_OUT
PWR
PWR
D_OUT
D_IN
D_IO,
A_IN
D_IO,
A_IN
D_IO,
A_IN
D_IO,
A_IN
D_IN
D_IN
D_OUT
1
Reserved. Tie this pin to ground, preferably with a 10 kΩ pull-down resistor.
Description
Output Clock Mode 0. With CLKMODE1, this pin sets the frequency of the CLKOUT signal.
PLL Mode Select Pin 2.
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
Regulator Drive. Supplies drive current for 1.8 V regulator. The base of the voltage regulator’s
external PNP transistor is driven from VDRIVE.
Crystal Oscillator Output. A 100 Ω damping resistor should be connected between this pin and the
crystal. This output should not be used to directly drive a clock to another IC; the CLKOUT pin
exists for this purpose. If the crystal oscillator is not used, the XTALO pin can be left unconnected.
Crystal Oscillator Input. This pin provides the master clock for the ADAU144x. If the ADAU144x
generates the master clock in the system, this pin should be connected to the crystal oscillator
circuit. If the ADAU144x is a slave to an external master clock, this pin should be connected to the
master clock signal generated by another IC.
Phase-Locked Loop Filter. Two capacitors and a resistor need to be connected to this pin as shown
in Figure 11.
Phase-Locked Loop Supply. Provides 3.3 V power supply for the PLL. This should be decoupled to
PGND with a100 nF capacitor.
Phase-Locked Loop Ground. Ground for the PLL supply. AGND, DGND, and PGND pins can be tied
directly together in a common ground plane. PGND should be decoupled to PVDD with a 100 nF
capacitor.
S/PDIF Input. Accepts digital audio data in the S/PDIF format. When not used, this pin can be left
disconnected.
S/PDIF Output. Outputs digital audio data in the S/PDIF format. When not used, this pin can be left
disconnected.
Analog Supply. 3.3 V analog supply for the auxiliary ADC. This pin should be decoupled to AGND
with a 100 nF capacitor.
Analog Ground. Ground for the analog supply. This pin should be decoupled to AVDD with a
100 nF capacitor.
Master Clock Output. Used to output a master clock to other ICs in the system. Set using the
CLKMODEx pins. When not used, this pin can be left disconnected.
Reset. Active-low reset input. Reset is triggered on a high-to-low edge and exited on a low-to-high
edge. For detailed information about initialization, see the Power-Up Sequence section.
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 3. When not used, this pin can
be left disconnected.
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 2. When not used, this pin can
be left disconnected.
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 1. When not used, this pin can
be left disconnected.
Multipurpose, General-Purpose IO/Auxiliary ADC Input 0. When not used, this pin can be left
disconnected.
Phase-Locked Loop Mode Select Pin 1.
Phase-Locked Loop Mode Select Pin 0.
Serial Data Port 0 Output. When not used, this pin can be left disconnected.
Rev. PrA | Page 12 of 92