adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 18

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

INITIALIZATION
Power-Up Sequence
The ADAU144x has a built-in initialization period, which
allows for sufficient time for the PLL to lock and the registers to
initialize their values. On a positive edge of RESET , the PLL settings
are immediately set by the PLL0, PLL1, and PLL2 pins, and the
master clock signal is blocked from the chip subsystems. The
initialization time lasts 10 ms, which is measured from the rising
edge of RESET . New values should not be written via the control
port until the initialization is complete.
Table 6 shows some typical times to boot the ADAU144x into
the operational state necessary for an application, assuming a
400 kHz I
parameter set, and all registers (9 kB) are loaded. In reality, most
applications use less than this full amount, and unused program
and parameter RAM need not be initialized, so the total boot
time may be shorter.
Recommended Program/Parameter Loading Procedure
When writing large amounts of data to the program or
parameter RAM in direct write mode, such as when
downloading the initial contents of the RAMs from an external
memory, the processor core should be disabled to prevent
unpleasant noises from appearing at the audio output. When
small amounts of data are transmitted during real-time
operation of the DSP, such as when updating individual
parameters, the software safeload mechanism can be used.
More information is available in the Software Safeload section.
Power-Reduction Modes
Sections of the ADAU144x chip can be turned on and off as
needed to reduce power consumption. These include the
ASRCs, S/PDIF receiver and transmitter, auxiliary ADCs, and
Table 6. Power-Up Time
PLL Lock Time (ms)
10
2
C clock or a 5 MHz SPI clock is used and a full program,
I
25
2
C (@ 400 kHz SCL)
Approximate Boot Time; Loading Maximum Program/Parameter/Registers (ms)
Rev. PrA | Page 18 of 92
2
SPI (@ 5 MHz CCLK)
DSP core. More information is available in the Master Clock
and PLL Modes and Settings section.
System Initialization Sequence
Before the IC can process audio in the DSP, the following initial­
ization sequence must be completed. (Step 5 through Step 11
can be performed in any order, as needed.)
1. Power on the IC and bring it out of reset. The order of the
2. Wait at least 10 ms for the initialization to complete.
3. Enable the master clocks of all modules to be used (see the
4. Deassert the core run bit (see the DSP Core Modes and
5. Set the serial input modes (see the Serial Input Port Modes
6. Set the serial output modes (see the Serial Output Port
7. Set the routing matrix modes (see details of Address
8. Set the DSP core rate select registers (see the DSP Core
9. Write the parameter RAM (Address 0x0000 to
10. Write the program RAM (Address 0x2000 to
11. Write all other necessary control registers, such as ASRCs
12. Assert the core run bit (see the DSP Core Modes and
power supplies (DVDD, IOVDD, and AVDD) does not
matter.
Master Clock and PLL Modes and Settings section).
Settings section).
Registers (Address 0xE000 to Address 0xE008) section).
Modes Registers (Address 0xE040 to Address 0xE049
section).
0xE080 to Address 0xE09B) in the Flexible Audio Routing
Matrix Modes section).
Rate Select Register (Address 0xE220) section).
Address 0x0FFF).
Address 0x2FFF).
and S/PDIF (Address 0xE221 to Address 0xE24C).
Settings section).
SPI (@ 25 MHz CCLK)
0.4
Total (ms)
10.4 to 35