adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 20

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

Table 7. PLL Modes
DSP Core Rate
Normal
Double
Quad
1
2
If the normal DSP core rate (f
48 kHz, then f
The PLL divider is set by the PLLx pins.
S,DUAL
1
is 96 kHz and f
Input to MCLK
(XTALI Pin)
64 × f
128 × f
256 × f
384 × f
512 × f
32 × f
64 × f
128 × f
192 × f
256 × f
16 × f
32 × f
64 × f
96 × f
128 × f
XTALI
S,NORMAL
S,NORMAL
S,DUAL
S,DUAL
S,QUAD
S,QUAD
S,QUAD
S,QUAD
S,QUAD
S,NORMAL
S,NORMAL
S,NORMAL
S,NORMAL
S,DUAL
S,DUAL
S,DUAL
S,QUAD
f
) is 44.1 kHz, the double DSP core rate (f
S,NORMAL
f
S,DUAL
f
S,QUAD
is 192 kHz.
× 32, 64, 128, 192, 256
× 64, 128, 256, 384, 512
× 16, 32, 64, 96, 128
PLL2
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
PLL MODE PINS
PLL1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
SELECT THE
PLL DIVIDER
PLL DIVIDER
(1, 2, 4, 6, 8)
Figure 10. Master Clock Signal Flow
÷
Rev. PrA | Page 20 of 92
PLL0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
S,DUAL
f
S,NORMAL
f
f
S,QUAD
S,DUAL
) is 88.2 kHz, and the quad DSP core rate (f
× 32
PLL
Divider
1
2
4
6
8
1
2
4
6
8
1
2
4
6
8
× 16
× 64
CORE CLOCK
MULTIPLIER
2
×
f
Core Clock
Multiplier
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
S,NORMAL
f
f
S,DUAL
S,QUAD
× 1792
× 896
× 3584
(NORMAL, DUAL, QUAD)
REGISTER 0xE220
DSP CORE RATE
SELECTS THE
Core Clock
(f
3584 × f
3584 × f
3584 × f
3584 × f
3584 × f
1792 × f
1792 × f
1792 × f
1792 × f
1792 × f
896 × f
896 × f
896 × f
896 × f
896 × f
S,QUAD
CORE
DSP
CORE
) is 176.4 kHz. Likewise, if f
)
S,QUAD
S,QUAD
S,QUAD
S,QUAD
S,QUAD
S,NORMAL
S,NORMAL
S,NORMAL
S,NORMAL
S,NORMAL
S,DUAL
S,DUAL
S,DUAL
S,DUAL
S,DUAL
Instructions per
Sample
3584
3584
3584
3584
3584
1792
1792
1792
1792
1792
896
896
896
896
896
S,NORMAL
is