adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 39

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

Word Length Bits (Bits[7:6])
These bits set the word length of the input data to 16, 20, or
24 bits. If the input signal has more data bits than this word
length, the extra bits are truncated. The fourth setting is flexible
TDM. For more information, see the Serial Input Flexible TDM
Interface Modes section.
MSB Position Bits (Bits[5:3])
These bits set the position of the MSB in the data stream.
TDM Type (Bits[2:0])
These bits set the number of channels contained in the data
stream. The possible choices are TDM2 (stereo), TDM4, TDM8
or flexible TDM, TDM16, and packed TDM4 mode. For more
information on the packed TDM4 mode, see the Packed TDM4
Mode section. If the word length bits (Bits[7:6]) are set to 11 for
flexible TDM mode, then TDM type bits (Bits[2:0]) must also
be set for flexible TDM mode (that is, set to 010).
In master mode, the ADAU144x can generate either an LRCLK
clock signal (50% duty cycle) or an LRCLK synchronization pulse
at the specified frequency (f
pulse is generated, its width is equal to one single internal BCLK.
Each channel requires 32 BCLK cycles per LRCLK. Therefore, for
TDM4, 128 BCLK cycles are required; for TDM8, 256 BCLK
cycles; for TDM16, 512 BCLK cycles; for TDM2, 64 BCLK cycles
(except when the LRCLK signal is a 50% duty cycle signal (that
is, not a pulse) or when it is running in I
and for packed TDM4, 64 BCLK cycles.
SERIAL OUTPUT PORTS
The serial output ports convert 16-, 20-, and 24-bit audio signals
coming from the audio processor to standard I
on the serial data outputs. They support TDM2, TDM4, TDM8,
and TDM16 time division multiplexing schemes and I
justified, right-justified, MSB delay-by-12 and delay-by-16 modes.
S,NORMAL
BCLK POLARITY
LRCLK POLARITY
SDATA_INx
SDATA_INx
LRCLKx
LRCLKx
, f
LRCLKx
LRCLKx
S,DUAL
BCLKx
BCLKx
2
S or left-justified mode);
, or f
2
S and TDM signals
S,QUAD
L
). When a
Figure 32. Serial Input LRCLK Polarity
Figure 31. Serial Input BCLK Polarity
2
S, left-
R
Rev. PrA| Page 39 of 92
L
Different clock polarities and multiple word lengths are supported,
as well as the capability to drive in master mode or to be driven
in slave mode.
The serial output ports are composed of up to nine clock domains
(Clock Domain 3 to Clock Domain 11) and up to nine serial
data signals (SDATA_IN0 to SDATA_IN8).
In slave mode, the nine serial output clock domains are driven
directly from the corresponding nine pairs of LRCLKx and
BCLKx pins on the IC. Three pairs of LRCLKx and BCLKx pins
(LRCLK[11:9] and BCLK[11:9]) are hardwired to Clock
Domains[11:9], which are serial outputs. The remaining six
pairs of LRCLKx and BCLKx pins (LRCLK[8:3] and
BCLK[8:3]) are multiplexed to Clock Domains[8:3] as either
inputs or outputs. The multiplexer can be set to use these
signals as output clock domains by writing to Bits[5:0] of the
clock pad multiplexer register (Address 0xE240) as explained in
Table 25. This configuration is also valid in master mode.
Table 25. Output Clock Domain Multiplexing
Clock Domain
0
1
2
3
4
5
6
7
8
Figure 33 shows in detail how the clocks are routed to and from
the serial output ports. For the assignable clock domains (Clock
Domains[8:3]), the clock pad multiplexer allows each clock
domain to be individually routed to either the serial input ports
or to the serial output ports. In slave mode, the clock domain
R
L
Chip Pins
LRCLK9, BCLK9
LRCLK10, BCLK10
LRCLK11, BCLK11
LRCLK3, BCLK3
LRCLK4, BCLK4
LRCLK5, BCLK5
LRCLK6, BCLK6
LRCLK7, BCLK7
LRCLK8, BCLK8
R
Register 0xE240 Setting
N/A
N/A
N/A
Set Bit 0 to 1
Set Bit 1 to 1
Set Bit 2 to 1
Set Bit 3 to 1
Set Bit 4 to 1
Set Bit 5 to 1