adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 32

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

Serial Clock Domains
There are 12 clock domains (pairs of LRCLKx and BCLKx pins)
available in the ADAU144x. Of these, three are available exclusively
to the serial data input ports, three are available exclusively to
the serial data output ports, and the remaining six can be assigned
to clock either input or output ports.
The ADAU1445, which contains two 8-channel ASRCs, and the
ADAU1446, which contains no ASRCs, do not require as many
clock domains as the ADAU1442. However, all clock domain
pins are available on every IC in the ADAU144x family. In a
system with no sample rate conversion and with serial ports in
slave mode, at least two pairs of LRCLKx and BCLKx pins must
be connected: one pair for the input serial ports and one pair
for the output serial ports. If all serial ports are in master mode
and synchronous, then only one pair or LRCLKx and BCLKx pins
need to be connected.
Figure 27 shows a simplified view of the assignment of clock
domains to the input and output sides of the chip. Note that
each clock domain is comprised of two signals, namely the
BCLK (bit clock) and LRCLK (frame clock). Therefore, the
12 clock domains contain a total of 24 clock signals.
Each clock domain is capable of acting as a master or slave. For
this reason, all LRCLK and BCLK pins are bidirectional. In slave
mode, the LRCLK and BCLK pins receive clock signals from an
external source, such as a codec. In master mode, the LRCLK
and BCLK pins output clock signals to external slave ICs.
MASTER/SLAVE
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SDATA_IN4
SDATA_IN5
SDATA_IN6
SDATA_IN7
SDATA_IN8
SELECT
Figure 27. Simplified Serial Clock Domain Assignment
SERIAL
PORTS
INPUT
(×9)
0 TO 2
2
6
2
2
Rev. PrA | Page 32 of 92
CLOCK DOMAINS
2
2
3 TO 8
(×12)
2
12
2
While a clock domain in slave mode can clock an arbitrary number
of serial ports, a clock domain in master mode can only clock a sin­
gle serial port. For Clock Domains[2:0] and Clock Domains[11:9],
the corresponding serial port is fixed as an input or output. For
assignable clock domains (Clock Domains[8:3]), the corresponding
serial port can be either an input or output, depending on the
setting of the clock pad multiplexer register (see Table 18 for
more details).
Table 18. Master Mode Clock Domain Assignment
Clock
Domain
0
1
2
3
4
5
6
7
8
9
10
11
1
2
Depends on the setting of the clock pad multiplexer register (Address 0xE240).
2
9 TO 11
2
OUTPUT
SERIAL
PORTS
(×9)
6
2
Chip Pins
LRCLK0, BCLK0
LRCLK1, BCLK1
LRCLK2, BCLK2
LRCLK3, BCLK3
LRCLK4, BCLK4
LRCLK5, BCLK5
LRCLK6, BCLK6
LRCLK7, BCLK7
LRCLK8, BCLK8
LRCLK9, BCLK9
LRCLK10, BCLK10
LRCLK11, BCLK11
2
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
Serial Port
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3 or SDATA_OUT3
SDATA_IN4 or SDATA_OUT4
SDATA_IN5 or SDATA_OUT5
SDATA_IN6 or SDATA_OUT6
SDATA_IN7 or SDATA_OUT7
SDATA_IN8 or SDATA_OUT8
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
1
1
1
1
1
1