peb2035 ETC-unknow, peb2035 Datasheet - Page 104

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

XTDS ... Transmit Test Data Sense
XCO2 ... XCO0 ... Transmit Clock-Slot Offset
Transmit Control 1 (WRITE)
XC1
SCLK ... Select System Clock
MCA ... Mask: CRC Alarm
XTO5 ... XTO0...Transmit Time-slot Offset
Receive Control 0 (WRITE)
RC0
ECE ... Enable CRC Counter Extension
Semiconductor Group
0 ... Outputs XTOP, XTOM are active low.
1 ... Outputs XTOP, XTOM are active high.
0 ... If the system clock at port SCLK is 4096 kHz.
1 ... If the system clock at port SCLK is 8192 kHz.
0 ... Normal operation. CRC errors are counted at status register CEC (8 bit length) with a
1 ... Extended CRC error counting with additional counter stages (bits CECX.CE8 and
Initial value loaded into the transmit bit counter at the trigger edge of SCLK when the
synchronous pulse at port SYPQ is active (see figure 6).
Only valid if extended multiframe is selected.
If this bit is set, the occurrence of a CRC error (one per multiframe maximum) triggers the
interrupt port AINT if enabled via CCR.AINT.
Initial value loaded into the transmit time-slot counter at the trigger edge of SCLK when the
synchronous pulse at port SYPQ is active (see figure 6).
A write access to this address resets the transmit speech memory to its basic starting
position. Therefore, updating the value should only be done when the ACFA is initialized or
when a transmit slip indicates a defective clock system.
maximum value of 255 (‘FF’ hex).
CECX.CE9, 10 bit counter). Maximum value is 1023 (‘3FF’ hex) which is also valid for
interrupt generation if enabled.
7
7
SCLK
ECE
RPYS
MCA
XTO5
1
DFRZ
104
RDIS
RCO2
RCO0
XTO0
0
0
PEB 2035
(07)
(08)