peb2035 ETC-unknow, peb2035 Datasheet - Page 95

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

CRC Error Counter Extension
CECX
CV8 … CV9 … Code Violation Counter Extension
CE8 … CE9 … CRC Error Counter Extension
Receive Sn-Bit Stack (READ)
RSN
RSN7 … RSN0 … Receive Sn-Bit Data (Y-Bits)
Semiconductor Group
If automatic transmission of sub-multiframe status is enabled by setting bit XSP.AXS, above
status information will be inserted automatically in S
multiframe (under the condition that time-slot 0 transparent modes are both disabled): SI1
S
Additional bits which increase CVC to a 10-bit counter. These bits are activated by setting
control bit EMOD.ECVE. For detailed information, refer to description of status register
CVC.
Additional bits which increase CEC to a 10-bit counter. These bits are activated by setting
control bit RC0.ECE. For detailed information on CRC counting, refer to description of status
register CEC.
If the Sn-bit stack mode is enabled by setting bits MODE.CRC = 1 and MODE.ENSN = 1, the
receive multiframe flag RSP.RFLG requests reading five bytes of Sn-bit information from
this stack. In addition, a receive multiframe begin interrupt may be generated by setting bits
CCR.AINT and XSP.MRMB.
Contents of the stack are updated with the service word information of the previously
received CRC multiframe (or previously received eight doubleframes). The first byte read
from this stack contains the information of the eight RY4-bits per multiframe (bit slot 8 of
every service word). RSN7 is received in frame 1, RSN0 in frame 15.
i
-bit of frame 13, SI2
7
7
RSN7
1
1
S
CV9
i
-bit of frame 15.
CV8
95
1
i
-bit position of every outgoing CRC
1
CE9
RSN0
CE8
0
0
PEB 2035
(0B)
(09)