peb2035 ETC-unknow, peb2035 Datasheet - Page 118

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Receive FS/DL Data (READ)
RFDL
RFD7 ... RFD0 ... Receive FS/DL Bits
CRC Error Counter Extension
CECX
CV8 ... CV9 ... Code Violation Counter Extension
CE8 ... CE9 ... CRC Error Counter Extension
Semiconductor Group
status
Only significant in F4, ESF and F72 format.
RFD5: DL bit of frame 11 (23), FS bit of frame n + 12
RFD4: DL bit of frame 9 (21), FS bit of frame n + 10
RFD3: DL bit of frame 7 (19), FS bit of frame n + 8
RFD2: DL bit of frame 5 (17), FS bit of frame n + 6
RFD1: DL bit of frame 3 (15), FS bit of frame n + 4
RFD0: DL bit of frame 1 (13), FS bit of frame n + 2
The microprocessor should read this register within 12 frames after request signal RMFB
goes active. The relationship to the multiframe structure is given by the bits MFR.RMB and
MFR.RRS. The bit-frame allocation in F4 format is not definite. Deactivation of port RMFB
is done by setting bit XFDL.RMAK.
Additional bits which increase CVC to a 10 bit counter. These bits are activated by setting
CVC.
Additional bits which increase CEC to a 10 bit counter. These bits are activated by setting
control bit RC0.ECE. For detailed information on CRC counting, refer to description of
register CEC.
control bit EMOD.ECVE. For detailed information, refer to description of status register
ESF format
7
7
1
1
1
1
RFD5
CV9
F72 format: n = 24, 36, 48, 60
F4 format: n = 0
CV8
118
1
1
CE9
RFD0
CE8
0
0
PEB 2035
(08)
(09)