peb2035 ETC-unknow, peb2035 Datasheet - Page 97

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

6.1
PCM 24 Control Registers
Common Control Register (WRITE)
CCR
AINT … Enable Alarm Interrupt Mode
FRS … Force Resynchronization
CRD ... Enable Control Register Read
CLR ... Clear Error Latches
SAIS ... Send AIS Towards System Interface
SRAF ... Select Remote Alarm Format for F12 and ESF Format
Semiconductor Group
0 ... Normal operation (status register read enabled).
1 ... Enables control register read.
0 ... F12: bit2 = 0 in every channel. ESF: pattern ‘1111 1111 0000 0000..‘ in data link channel.
1 ... F12: FS bit of frame 12. ESF: bit2 = 0 in every channel
Register Definitions
Setting this bit switches the output: FREEZS to the alarm interrupt function (AINT).
Acknowledging is done by setting the bit LOOP.AIA. Programming the mask register MASK
and the additional bit XC1.MCA selects the interrupt sources.
A transition from low to high will force the frame aligner to execute a resynchronization of the
pulse frame. In the asynchronous state, a new frame position is assumed at the next
candidate if there is one. Otherwise, a new frame search with the meaning of a general reset
is started. In the synchronous state this bit will have the same meaning as bit CCR.EXLS.
This bit has to be set 1 s before reading the error counters FEC, CVC, or CEC. Errors
occuring during setting and resetting of this bit will be ignored. The error indications
RSR.SLPP, RSR.SLPN, ASR.RPE, ASR.XPE, ASR.XSLP, MFR.DSLP, and MFR.GPE are
also cleared when CLR is reset.
Send AIS via output RDO towards system interface. This function is not influenced by bit
EMOD.DAIS.
7
AINT
FRS
CRD
CLR
97
SAIS
SRAF
EXLS
SIM
0
PEB 2035
(00)