peb2035 ETC-unknow, peb2035 Datasheet - Page 88

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

IC1 … IC32 … Idle Channel Selection Bits
Note: Although time-slot 0 can be selected via bit IC1, its content is only altered if one of the
PCM 30 Status Registers
Receive Status Register (READ)
RSR
NOS … No Signal Indication
AIS … Alarm Indication Signal
Semiconductor Group
0 … Normal operation.
1 … Idle channel mode. The content of the selected time-slot is overwritten by the idle channel
transparent modes is selected (XSP.TT0, XSP.TT0S or EMOD.TT0X).
These bits define the channels (time-slots) of the outgoing PCM frame to be altered.
Assignments:
IC1
IC2
IC32
code defined via register IDLE.
This bit is set when
– 3 or less ones are received in a time interval of 250 s, or
– a receive route clock pulse (port RRCLK) fails to occur in a time interval of 4 internal SCLK
clock cycles (4096 kHz).
The bit will be reset when no alarm condition is detected. The bit will also be set during alarm
simulation and reset if CCR.SIM is cleared and no alarm condition exists.
After resynchronization has been regained (RSR.LOS = 0), NOS should be ignored for
250 s.
This bit is set when two or less zeros in the received bit stream are detected in a time interval
of 250 s. The bit will be reset when no alarm condition is detected.
The bit will also be set during alarm simulation and reset if CCR.SIM is cleared and no alarm
condition exists.
After resynchronization has been regained (RSR.LOS = 0), AIS should be ignored for
250 s.
time-slot 0
time-slot 1
7
time-slot 31
NOS
AIS
LOS
RRA
88
SLP
RPE
CAL
SDI
0
PEB 2035
(00)