peb2035 ETC-unknow, peb2035 Datasheet - Page 13

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

1.3
P-LCC
Pin No.
18
19
20
21
22
25
26
27
28
29
Semiconductor Group
Pin Definitions and Functions (cont’d)
P-DIP
Pin No.
16
17
18
19
20
21
22
23
24
25
Symbol
A0
A1
A2
A3
RDQ
WRQ
CEQ
COS
SCLK
RRCLK
Input (I)
Output (O)
I
I
I
I
I
I
I
I
I
I
Function
Address Bus
These inputs interface with four lines of the
system’s address bus to select one of the internal
registers. Write access to address ’0E’ and ’0F’ is
not allowed.
Read Enable (active low)
This signal indicates a read operation. If both CEQ
and RDQ are active, status information of the
registers selected via A0 … A3 will be read from
the ACFA. If access to the internal signaling
stacks is enabled by setting bit XC0.ISIG, the data
from the stack: RSIG may be read when ACKNLQ
and RDQ are active.
Write Enable (active low)
This signal indicates a write operation. If both CEQ
and WRQ are active control information may be
written to the registers selected via A0 … A3. If
access to the internal signaling stacks is enabled
by setting bit XC0.ISIG data may be written to the
stack XSIG when ACKNLQ and WRQ are active.
Chip Enable (active low)
A low signal enables normal read/write access to
the internal registers.
Carrier Out of Service
A high signal at this input enables transmission of
AIS via outputs XDOP, XDOM, and XOID without
any framing structure.
System Clock
Working clock for the ACFA with a frequency of
4096 kHz or 8192 kHz (selected by bit MODE.
SCLK)
Receive Route Clock
Extracted from the incoming data pulses by the
line interface unit (e.g. IPAT, PEB 2235/PEB
2236).
Clock frequency: 2048 kHz [PCM 30]
13
1544 kHz [PCM 24]
PEB 2035