peb2035 ETC-unknow, peb2035 Datasheet - Page 132

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

9
Additional Features of ACFA, Version 4
Additions to PCM 30 mode
Semiconductor Group
CRC Alarm Interrupt
As an extension of the alarm interrupt capabilities, the occurrence of a CRC error can be defined
as interrupt source (XC1.MCA) for triggering interrupt port AINT.
Idle Code Insertion
In transmit direction, the contents of selectable channels (time-slots) can be overwritten by the
pattern defined via register IDLE. The selection of ‘idle channels’ is done by programming the
four-byte register bank ICB1 ... ICB4 (enabled via CPY.SW).
Selectable Conditions for Loss of Synchronization
Asynchronous state is reached either after three or after four consecutive incorrect FAS/service
words (bit RC1.ASY4). Additionally, the service word condition can be disabled (bit RC1.SWCD).
Multiframe Force Resynchronization
A search for a new multiframe alignment can be initiated via bit MODE.MFCS without influence
on doubleframe synchronous state.
Automatic Force Resynchronization
A search for doubleframe alignment is automatically initiated if two multiframe pattern with a
distance of n
alignment has been regained (bit MODE.AFR).
Submultiframe Error Indication Counter
If programmed via bit EMOD.ESEI, counter CVC (8 or 10 bits) counts zeros in Si-bit position of
frame 13 and 15 of every received CRC multiframe. This counter option gives information about
the outgoing transmit PCM line if the Si bits are used by the remote end for submultiframe error
indication.
Code Violation Counter Extension
The counter CVC can be switched to 10-bit length via bit EMOD.ECVE (status bits CECX.CV8
and CECX.CV9). This is useful for extended submultiframe error indication counting.
Full Bauded Mode
Output pins XDOP, XDOM can be switched to full bauded mode via bit EMOD.XFB.
Extended DMA Mode
DMA request lines RREQ, XREQ remain active until the second read/write access to the
assigned stack is provided (bit EMOD.EDMA).
Disable AIS to System Interface
Automatic transmission of AIS to system internal highway (RDO) during asynchronous state can
be disabled via bit EMOD.DAIS. However, it remains programmable via bit CCR.SAIS.
Time-Slot 0 Extended Signaling Transparent Mode
Enabled via EMOD.TT0X this new mode provides transparency in transmit direction only for Sn
bits.
Annex
2 ms have not been found within a time interval of 8 ms after doubleframe
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PEB 2035