peb2035 ETC-unknow, peb2035 Datasheet - Page 26

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

are received during the next CRC (sub-)multiframe. If there is at least one mismatch, the CRC error
counter will be incremented. As addition, this 8-bit counter (default) can be extended to 10-bit
length.
As an extension of the alarm interrupt capabilities, the occurrence of a CRC error can be defined as
interrupt source for triggering interrupt port AINT.
Receive Speech Memory
The speech memory is organized as a two-frame elastic buffer with a size of 64
48
The functions are:
Controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-
parallel, channel-serial data which is circularly written to the speech memory using the Receive
Route Clock (RRCLK). At the same time, a parity signal is generated over each channel and also
stored in the speech memory.
Reading of stored data is controlled by the System Clock (SCLK) and the Synchronous Pulse
(SYPQ) in conjunction with the programmed offset values for the receive time-slot/clock-slot
counters. After conversion into a serial data stream and parity checking (errors are reported via the
status registers), the data is given out via port RDO. Channel parity information is output at port
RCHPY with selectable output sense. In PCM 24 mode, two channel translation modes are
provided. Unequipped time-slots will be set to ’FF’ hex. For both PCM modes, two bit rates (2048/
4096 kbit/s) are selectable via the microprocessor interface.
Figure 3 gives an idea of operation of the receive speech memory:
A slip condition is detected when the write pointer (W) and the read pointer (R) of the memory are
nearly coincident, i.e. the write pointer is within the slip limits (S +, S –). The values of S + and S –
depend on the selected PCM mode, on the channel translation mode and on the value of bit
ACR.SLM. If a slip condition is detected, a negative slip (the next received frame is skipped) or a
positive slip (the previous received frame is read out twice) is performed at the system interface,
depending on the difference between RRCLK and SCLK, i.e. on the position of pointer R and W
within the memory.
Semiconductor Group
Clock adaption between system clock (SCLK) and route clock (RRCLK).
Compensation of input wander and jitter. Maximum of wander amplitude (peak-to-peak):
PCM 30: 190 UI (1 UI = 488 ns)
PCM 24: 126 UI in channel translation mode 0 (bit ACR.SLM reset)
For detailed information on the channel translation modes.
Frame alignment between system frame and receive route frame
Reporting and controlling of slips
9 bit (PCM 24) 9 bit include 8-bit channel data plus one parity bit.
142 UI in channel translation mode 0 (bit ACR.SLM set)
(1 UI = 644 ns)
78 UI in channel translation mode 1
26
9 bit (PCM 30) or
PEB 2035