peb2035 ETC-unknow, peb2035 Datasheet - Page 113

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Framing Error Counter (READ)
FEC
FE7 ... FE0 ... Framing Errors
Code Violation Counter (READ)
CVC
CV7 ... CV0 ... Code Violations
Semiconductor Group
This 8-bit counter will be incremented when incorrect FT and FS bits in F4, F12 and F72
format or incorrect FAS bits in ESF format are received. A counter overflow will be inhibited.
During alarm simulation, the counter will be incremented twice. Disabling the counter is
done by setting the bit CCR.CLR. Clearing is done by resetting it.
No function if optical interface mode has been enabled.
If the dual rail input mode is selected (bit MODE.OPT = 0), the 8-bit counter will be
incremented by detecting violations in the B8ZS mode (MODE.CODE = 1) which are not
due to zero substitution. If simple AMI coding is enabled (MODE.CODE = 0) all bipolar
violations are counted. A counter overflow will be inhibited.
During alarm simulation, the counter will be incremented continuously with every second
received bit up to its saturation. Disabling the counter is done by setting bit CCR.CLR;
clearing is done by resetting it.
As extension to this 8-bit counter, two stages (CECX.CV8, CECX.CV9) may be added to get
a 10 bit counter with a maximum value of 1023 (3FF hex). This counter mode is enabled by
setting bit EMOD.ECVE. All other features are the same as for 8-bit counting.
7
FE7
7
CV7
113
CV0
FE0
0
0
PEB 2035
(01)
(02)