peb2035 ETC-unknow, peb2035 Datasheet - Page 82

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Transmit Control 1 (WRITE)
Value after RESET: 00
XC1
SCLK … Select System Clock
MCA … Mask: CRC Alarm
XTO5 … XTO0 … Transmit Time-Slot Offset
Receive Control 0 (WRITE)
Value after RESET: 30
RC0
ECE … Enable CRC Counter Extension
RPYS … Receive Parity Sense
RDIS … Receive Data Input Sense
Semiconductor Group
0 … If the system clock at port SCLK is 4096 kHz.
1 … If the system clock at port SCLK is 8192 kHz.
0 … Normal operation. CRC errors are counted at status register CEC (8-bit length) with a
1 … Extended CRC error counting with additional counter stages (bits CECX.CE8 and
0 … Even parity.
1 … Odd parity.
0 … Inputs RDIP, RDIM are active low, input ROID is active high.
1 … Inputs RDIP, RDIM are active high, input ROID is active low.
Only valid if CRC multiframe is selected.
If this bit is set, the occurrence of a CRC error (one per submultiframe maximum) triggers
the interrupt port AINT if enabled via CCR.AINT.
Initial value loaded into the transmit time-slot counter at the trigger edge of SCLK when the
synchronous pulse at port SYPQ is active (see figure 6).
maximum value of 255 (‘FF’ hex).
CECX.CE9, 10 bit counter). Maximum value is 1023 ‘3FF’ hex) which is also valid for
interrupt generation if enabled.
7
7
SCLK
ECE
H
H
RPYS
MCA
XTO5
1
1
82
RDIS
RCO2
RCO0
XTO0
0
0
PEB 2035
(07)
(08)