peb2035 ETC-unknow, peb2035 Datasheet - Page 85

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Alarm Interrupt Mask Register (WRITE)
Value after RESET: 00
MASK
MLOS … Mask: Loss Of Synchronization
MAIS …
MNOS … Mask: No Signal
MRRA … Mask: Receive Remote Alarm
MSLP … Mask: Receive Slip Indication
MCEC … Mask: CRC Error Counter Saturation
MFEC … Mask: Framing Error Counter Saturation
MCVC … Mask: Code Violation Counter Saturation
Idle Channel Code Register (WRITE)
Value after RESET: 54
IDLE
IDL7 … IDL0 … Idle Channel Code
Semiconductor Group
If the alarm interrupt mode is enabled via bit CCR.AINT this mask register selects the alarm
sources:
Mask bit = 0: alarm source disabled.
Mask bit = 1: alarm source enabled.
Assigned alarms will cause an interrupt signal at port AINT. Acknowledging is done by
writing a ‘1’ to the bit LOOP.AIA. Triggering a new interrupt by the same source is possible
only after this source has been inactive.
If channel loop back is enabled by programming the register LOOP, the contents of the
assigned outgoing channel at ports XDOP, XDOM, XOID is set equal to the idle channel
code selected by this register.
Additionally, the specified pattern overwrites the contents of all channels selected via the
idle channel register bank ICB1 … ICB4.
Its initial value (54 Hex) may be overwritten via the microprocessor interface.
Mask: Alarm Indication Signal
7
7
MLOS
IDL7
H
H
MAIS
MNOS MRRA MSLP MCEC MFEC MCVC
85
IDL0
0
0
PEB 2035
(0C)
(0D)