peb2035 ETC-unknow, peb2035 Datasheet - Page 75

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

The control registers are normally only writeable. In a test mode they may be read by setting bit
CCR.CRD (exceptions: bits LOOP.AIA, XSN7 … 0, XFDL.XMAK, XFDL.RMAK).
The status registers are only readable and are updated by the ACFA.
Register Definitions
PCM 30 Control Registers
Common Control Register (WRITE)
Value after RESET: 00
CCR
AINT … Enable Alarm Interrupt Mode
EXTD … Extended HDB3 Error Detection
four
CRD … Enable Control Register Read
CLR … Disable/Clear Error Counters
SAIS … Send AIS Towards System Interface
CCPY … Clear Channel Parity Alarm Latch
Semiconductor Group
0 … Only double violations are detected.
1 … Extended code violation detection: 0000 strings are detected additionally. Thereafter,
0 … Normal operation (status register read enabled).
1 … Enables control register read.
Setting this bit switches the output DFPY to the alarm interrupt function (AINT).
Acknowledging is done by setting bit LOOP.AIA. Programming the mask register MASK
and the additional bits XSP.MXMB, XSP.MRMB and XC1.MCA selects the interrupt
sources.
Selects error detection mode.
zeros.
This bit must be set 1 s before reading the error counters FEC, CVC, CEC. Clearing the
bit will reset these counters and the DMA slip indication (RSP.DSLP). Errors will be ignored
while this bit is active.
Send AIS via output RDO towards system interface. This function is not influenced by
bit EMOD.DAIS.
A ‘1’ resets the parity alarm flags: RSR.RPE, RSP.GPE, RSR.XPE.
incrementation of Code Violation Counter CVC is first done after receiving an additional
7
AINT
H
EXTD
CRD
CLR
75
SAIS
CCPY
FRS
SIM
0
PEB 2035
(00)