peb2035 ETC-unknow, peb2035 Datasheet - Page 105

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

RPYS ... Receive Parity Sense
DFRZ ... Disable Freeze Signal
RDIS ... Receive Data Input Sense
RCO2 ... RCO0 ... Receive Clock-Slot Offset
Receive Control 1 (WRITE)
RC1
SLC ... Select Loss of Sync Conditions
RRAM ... Receive Remote Alarm Mode
Semiconductor Group
0 ... Even parity.
1 ... Odd parity.
0 ... Inputs: RDIP, RDIM active low.
1 ... Inputs: RDIP, RDIM active high.
F4:
F12, F72: SSP = 0:
ESF:
RRAM = 0
Detection
F4:
F12:
ESF:
If high the synchronization status signal at port FREEZS is disabled.
Initial value loaded into the receive bit counter at the trigger edge of SCLK when the
synchronous pulse at port SYPQ is active (see figure 5).
Loss of synchronization (RSR.LOS or opt. FSR.MLOS) is declared if
SLC = 0 : 2 out of 4
SLC = 1 : 2 out of 5
framing bits are incorrect. It depends on the selected multiframe format and optionally on bit
EMOD.SSP which framing bits are observed:
The conditions for remote alarm (RSR.RRA) detection can be selected via this bit to allow
detection even in the presence of BER 10**-3:
– CCR.SRAF = 0: bit2 = 0 in every speech channel per frame.
– CCR.SRAF = 1: S-bit of frame 12 is forced to ‘1’
– CCR.SRAF = 0: pattern ‘1111 1111 0000 0000 ...’ in data link channel
– CCR.SRAF = 1: bit2 = 0 in every speech channel
SSP = 1:
7
SLC
RRAM RTO5
FT bits
FT bits
FT
FS
ESF framing bits
bit2 = 0 in every speech channel per frame.
RSR.LOS
FSR.MLOS
RSR.LOS
RSR.LOS: FS bits
105
RSR.LOS
RSR.LOS and FSR.MLOS
RTO0
0
PEB 2035
(09)