peb2035 ETC-unknow, peb2035 Datasheet - Page 28

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

2. Transmit Path
The inverse functions are performed for the transmit direction.
The PCM data is received from the system internal highway at port XDI with 2048 kbit/s or
4096 kbit/s. The channel assignment is equivalent to the receive direction. All unequipped time-
slots will be ignored.
The contents of selectable channels (time-slots) can be overwritten by the pattern defined via
register IDLE. The selection of ’idle channels’ is done by programming the three/four-byte register
bank ICB1 … ICB3, ICB4.
In PCM 24 mode, additional signaling information can be provided on a separate input (XSIG).
Internal multiplexing of (speech) data and signaling data can be disabled on a per channel basis
(Clear Channel Capability). This is also valid when using the internal signaling stack.
Latching of data is controlled by the System Clock (SCLK) and the Synchronous Pulse (SYPQ) in
conjunction with the programmed offset values for the Transmit Time-slot/Clock-slot Counters.
Transmit Speech Memory
The transmit speech memory is operational only in the PCM 24 mode. This one-frame elastic buffer
with a size of 24 9 bit (8 bit channel data plus 1 parity bit) serves as a temporary store for the PCM
data to adapt the system clock (SCLK) to the externally generated Transmit Route Clock (XRCLK),
and to re-translate channel structure used in the system to that of the line side. Its optimal start
position is initiated when programming the above offset values. Normally, XRCLK has to be phase
locked to a common submultiple of SCLK such as 8 kHz. A difference in the effective data rates of
system side and transmit side may lead to an overflow/underflow of the transmit speech memory:
thus, errors in data transmission to the remote end may occur. This error condition (transmit slip) is
reported to the microprocessor via the status registers. It signals that the external clock generation
is defective.
Maximum wander amplitude in PCM 24 mode (peak-to-peak):
(1 UI = 644 ns)
Because this is, under normal circumstances, a rare error condition no automatic action is taken by
the transmit speech memory as opposed to the receive speech memory in the case of a positive or
negative slip. In this case the ACFA requires a re-initialization of the transmit memory by re-
programming of the transmit time-slot counter. After that, this memory has its optimal start position.
In PCM 30 mode, the Transmit Route Clock (XRCLK) is derived directly from the system clock by
an internal clock divider. Consequently, the data received from the system interface is switched
through without the need of intermediate storage.
The parity generation/checking mechanism is symmetrical to the receive path. The channel data is
checked with the channel parity information generated internally or externally (input at port XCHPY
with selectable input sense). Errors are reported to the microprocessor interface. To avoid
difficulties with external parity generation, the parity signal for non-speech data (e.g. signaling data
or channels with bit robbing information) is computed internally.
Semiconductor Group
Channel translation mode 0: 58 UI
Channel translation mode 1: 46 UI
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PEB 2035