peb2035 ETC-unknow, peb2035 Datasheet - Page 67

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

PEB 2035
For the transmit path, the parity bit may optionally be input over pin XCHPY rather than being
generated internally (enabled via bit XC0.EPY; input sense selection via bit XC0.EPYS). This parity
bit should be fed in simultaneously with bit 8 (LSB) of the corresponding time-slot.
The use of the internal parity generator for the transmit path makes sense only for PCM 24 systems,
since for PCM 30 the transmit memory is not operational. An externally generated parity bit
(XCHPY) on the contrary, may provide means for monitoring system internal PCM paths for
malfunctions, both in PCM 30 and PCM 24 systems.
The parity bit generated at the input of the receive speech memory is output at port RCHPY
simultaneously with the corresponding time-slot. The output sense is selectable by bit RC0.RPYS.
Loopback of Time-Slots
Each of the 31 (24) channels may be selected for loopback from the system PCM input (XDI) to the
system PCM output (RDO). This loopback is programmed for one channel at a time selected by
register LOOP. In PCM 24 mode, it is possible to enable loop back of ‘pure’ channel data which is
input at port XDI, without signaling information supplied at port XSIG (bit LOOP.SLB). This function
is permitted in all signaling modes (CCS, CAS-CC and CAS-BR). During loopback, an idle channel
code programmed in register IDLE is transmitted to the remote end in the corresponding PCM route
channel.
For the channel test, sending sequences of test patterns like a 1-kHz check signal should be
avoided. Otherwise, an increased occurrence of slips in the tested channel will disturb testing.
These slips do not influence the other channels and the function of the receive memory. The usage
of a quasi-static test pattern is recommended.
Processor Interface Test
Testing the processor interface will not affect the normal operation of the device. The normally write
only control registers may be read in a test mode by setting bit CCR.CRD (except for all
acknowledge bits and the PCM 30 S
-bit stack).
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Diagnostic of Receive Speech Memory
The receive speech memory may be tested in the PCM 30 mode by an even parity bit generated
over a doubleframe. The doubleframe parity signal is output via pin DFPY.
Diagnostic Loopback
The test outputs XTOP and XTOM give a replica of the normal PCM route outputs and thus enable
monitoring of possible malfunctions of the transmission path, even during normal operation. A
diagnostic loopback of data may be implemented externally over XTOP and XTOM. During
diagnostics, transmission of AIS over XDOP and XDOM (XOID) should be initiated by setting port
COS to ‘1’ or setting bit MODE.XAIS to indicate that the PCM route is not available for normal use.In
applications with PEB 2235, PEB 2236, IPAT, as the line interface unit for the ACFA, diagnostic
loops to remote end and to system internal highway are performed without the need of any
additional hardware.
Semiconductor Group
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