peb2035 ETC-unknow, peb2035 Datasheet - Page 42

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Figure 4 gives an overview of influences on synchronization status for the case of different external
actions. Activation of auto-mode and non-auto-mode is performed via bit GSR.AUTO. Generally, for
initiating resynchronization it is recommended to use bit: CCR.EXLS first. In case where the
synchronizer remains in the asynchronous state, bit CCR.FRS may be used to enforce it to lock
onto the next framing candidate, although it might be a simulated one.
General Alarms
Channel Assignment
Two possibilities are provided for converting the 24 speech channels to the 32 time-slots on the
system internal highway (refer to section Interface to System Internal Highway). The selection is
performed via bit MODE.CTM. Transparent mode setting bit GCR.TM switches the ACFA in
transparent mode:
– In transmit direction bit 8 of the FS/DL time-slot from the system internal highway (XDI) is
inserted
– In receive direction the framing bit is also forwarded to RDO and inserted in the FS/DL time-slot.
General Signaling
For data link or signaling applications, it may be necessary to have external access to the FS bits
(F4 and F72 format) or to the DL bits of the extended superframe. Two methods of access are
provided:
Simultaneous use of both of these modes is permitted. For this application, FS/DL subchannels for
transmit direction may be programmed on a bit-by-bit basis over 12 frames via the additional mask
register FMR. They are accessed via the microprocessor interface while the other subchannels are
passed transparently from the system internal highway to the FS/DL-bit position of the assigned
outgoing 193-bit frame.
A combination of the two accessing methods only makes sense when using the more complex
multiframing formats (ESF, F72) to get a defined FS/DL subchannel assignment. For the 4-frame
multiframe structure, all mask bits are normally to be set to the same logical level.
Additional Support: 4-kHz DL clock
If programmed via bit ACR.DLC, ports RCHPY and XCHPY provide signals which mark the DL-bit
position within the data stream at RDO and XDI.
Semiconductor Group
AIS: Detection is flagged by bit RSR.AIS. Transmission is enabled via port COS or bit
MODE.XAIS.
NOS: Detection is flagged at bit RSR.NOS.
RAI: Remote Alarm Indication is flagged at bit RSR.RRA. Transmission is enabled via bit
GCR.XRA. The type of remote alarm indication depends on the selected multiframe format.
in the F-bit position of the outgoing frame.
Bit RDCF (bit 1 of FS/DL time-slot) indicates a DL bit.
in a defined FS/DL time-slot of the PCM data stream on the system internal highway
by reading and writing special registers via the microprocessor interface (RFDL, XFDL).
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PEB 2035