peb2035 ETC-unknow, peb2035 Datasheet - Page 37

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Organization of the Stacks
The sequently received S
are re-organized to bytes containing the S
The S
Moreover, S
enables transparency for S
Table 4
Organization of the Sn-Bit Stacks
Semiconductor Group
The standard procedure allows reading/writing the S
support. The S
The advanced procedure, enabled via bit MODE.ENSN, allows reading/writing two S
RSN, XSN with a size of 5 bytes. The two status bits RSP.RFLG and RSP.XFLG require
updating the stack information by reading/writing five bytes per multiframe from/to the assigned
stack address.To avoid loss of information, the status bits should be monitored at time intervals
less than 2 ms (1.5 ms recommended). With the first access to a stack, the associated status bit
will be reset.
Additionally, a transmit or receive multiframe begin interrupt is provided if alarm interrupt mode
is enabled (CCR.AINT) and bits XSP.MXMB or XSP.MRMB are set.
a8
byte is the first byte to read or to write via the microprocessor interface (refer to table 4).
a
bits may be processed via the system interface. Setting bit XSP.TT0S or EMOD.TT0X
a
-bit information will be updated every other frame.
Frame
Number
a
bits (S
n
11
13
15
1
3
5
7
9
bits in transmit direction (refer to table 3).
Slot
Bit
a4
S
S
4
a4
a4
.
.
.
up to S
S
S
5
a5
a5
.
.
.
a
S
S
-information of the same level (S
a5
6
a6
a6
.
.
.
) of odd numbered frames of the multiframe structure
S
S
7
a7
a7
.
.
.
37
S
S
8
a8
a8
.
.
.
a
-bit registers RSW, XSW without further
Microprocessor
Interface
D7
D0
.
.
a4
byte up to S
PEB 2035
a
-bit stacks
a8
byte).