peb2035 ETC-unknow, peb2035 Datasheet - Page 91

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

CV7 … CV0 … Code Violations
CRC Error Counter (READ)
CEC
CE7 … CE0 … CRC Errors
Semiconductor Group
The function of this counter depends on bit EMOD.ESEI:
ESEI = 0: No function if optical interface mode has been enabled.
If the dual rail input mode is selected (bit MODE.OPT = 0), the 8-bit counter will be
incremented when violations of the HDB3 code are detected. The error detection mode is
determined by programming the bit CCR.EXTD. A counter overflow will be inhibited.
During alarm simulation, the counter is incremented every four bits received up to its
saturation. Disabling the counter is done by setting bit CCR.CLR; clearing is done by
resetting it.
As extension to this 8-bit counter, two stages (CECX.CV8, CECX.CV9) may be added to get
a 10-bit counter with a maximum value of 1023 (3FF hex). This counter mode is enabled by
setting bit EMOD.ECVE. All other features are the same as for 8-bit counting.
ESEI = 1: If doubleframe format is selected, CVC has no function. If CRC-multiframe mode
is enabled, CVC now works as submultiframe error indication counter (8 or 10 bits) which
counts zeros in Si-bit position of frame 13 and 15 of every received CRC multiframe. There
is no difference in comparison to other counters for reading and resetting this counter and
interrupt generation in case of counter overflow.
– No function if doubleframe format is selected.
– In CRC-multiframe mode, the 8-bit counter will be incremented when a CRC-
submultiframe has been received with a CRC error. CRC errors will not be counted during
asynchronous state. A counter overflow will be inhibited.
During alarm simulation, the counter is incremented once per submultiframe up to its
saturation. Disabling the counter is done by setting the bit CCR.CLR and clearing is done by
resetting it.
As extension to this 8-bit counter, two stages (CECX.CE8, CECX.CE9) may be added to get
a 10-bit counter with a maximum value of 1023 (3FF hex). This counter mode is enabled by
setting bit RC0.ECE. All other features are the same as for 8-bit counting.
7
CE7
91
CE0
0
PEB 2035
(03)