peb2035 ETC-unknow, peb2035 Datasheet - Page 93

no-image

peb2035

Manufacturer Part Number
peb2035
Description
Communications Advanced Cmos Frame Aligner
Manufacturer
ETC-unknow
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2035
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
peb2035N
Manufacturer:
SIEMENS
Quantity:
25
Part Number:
peb2035N
Manufacturer:
INFINEON
Quantity:
5 510
Part Number:
peb2035N
Manufacturer:
MIENENS
Quantity:
20 000
Part Number:
peb2035N
Quantity:
50
Part Number:
peb2035N-V4.1
Manufacturer:
SIMENS
Quantity:
20 000
Part Number:
peb2035N-VA3
Manufacturer:
SIMENS
Quantity:
20 000
Part Number:
peb2035NV4.1
Manufacturer:
SIEMENS
Quantity:
5 076
Part Number:
peb2035NV4.1
Manufacturer:
SIEMENS
Quantity:
5 087
Part Number:
peb2035NV4.1
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
peb2035P
Manufacturer:
SIEMENS
Quantity:
5 510
Part Number:
peb2035P
Manufacturer:
SIEMENS
Quantity:
1 000
Part Number:
peb2035P
Manufacturer:
INFINEON
Quantity:
1 000
RFLG … Receive Multiframe Flag
DSLP … DMA Request Slip
GPE … Global Parity Error
XPE … Transmit Parity Error
RSIF … Receive Spare Bit for International Use (FAS Word)
RS13 … Receive Spare Bit (Frame 13, CRC Multiframe)
RS15 … Receive Spare Bit (Frame 15, CRC Multiframe)
Semiconductor Group
No function if standard doubleframe format is enabled (MODE.CRC = 0, ref. to
EMOD.DFSN). If MODE.CRC is set to one, this bit is set in (multiframe) synchronous state
at the beginning of every received CRC multiframe (or every eighth received doubleframe).
It is cleared
– with the first read access to the stack RSN, or
– automatically with beginning of frame 15 of every received CRC multiframe (this is valid
only if EMOD.DFSN = 0). In that case, a read access to the stack and to Si bits should be
avoided. Stack RSN and Si bits RSP.RS13 and RSP.RS15 will be updated with beginning
of every CRC multiframe (or every eighth doubleframe). RSP.RFLG should be monitored
continuously at time intervals less than 2 ms (1.5 ms recommended) to receive correct
Sn/Si-bit information.
If the use of the signaling stacks RSIG and XSIG is enabled by setting bit XC0.ISIG, this flag
is set if access to one of these stacks (2 bytes) is not completed before a new assigned
request occurs. The flag is cleared by setting bit CCR.CLR.
Set by a parity error in any transmit or receive channel. Cleared by bit CCR.CCPY.
The bit will be set during alarm simulation.
If channel parity check is enabled by programming register CPY this bit is set after a transmit
channel parity error occurs in the selected channel. This flag is meaningful only when the
external transmit channel parity input XCHPY is used (enabled by setting bit XC0.EPY). The
flag is set during alarm simulation.
First bit in FAS-word. Used only in doubleframe format, otherwise fixed to ‘1’.
First bit in service word of frame 13. Significant only in CRC-multiframe format, otherwise
fixed to ‘0’. This bit is updated with beginning of every received CRC multiframe (refer to
RSP.RFLG and XSP.MRMB).
First bit in service word of frame 15. Significant only in CRC-multiframe format, otherwise
fixed to ‘0’. This bit is updated with beginning of every received CRC multiframe (refer to
RSP.RFLG and XSP.MRMB).
93
PEB 2035

Related parts for peb2035