mt90226ag ETC-unknow, mt90226ag Datasheet - Page 12

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

12
MT90226 Pin Description (continued)
AE7,AD7,AC7,
AE8,AD8,AF7,
AE5,AD5,AE4,
AF3,AD4,AE3,
AF6,AD6,AF5,
AE12,AC12,
AC11,AD11,
AF10,AE10,
AF11,AE11,
AD10,AF9,
AE9,AD9
AD13
AC26
AD17
Pin #
AF12
AE13
AE21
AE19
W25
AC9
AF2
R23
U25
Y23
L1,
L2,
L4,
L3,
K1
J3
URxAddr
URxClav
up_r/w
Name
up_wr
up_oe
up_irq
up_cs
[15:0]
up_rd
DSTo
[11:0]
up_d
up_a
[4:0]
[14]
[12]
[10]
[8]
[6]
[4]
[2]
[0]
or
or
I/O
I/O Processor Data Bus. Data Bus to exchange data between the MT90226 and
O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY
O Processor Interrupt Request. Open drain signal. If this signal is low, the
O Serial TDM Data Output. Serial stream which contains transmit data. The
I
I
I
I
I
environment, URxClav is an active high tri-stateable signal from the MT90226
to ATM LAYER device.
Receive Address. Five bit wide address bus driven from the ATM to PHY
device to select the appropriate PHY address. URxAddr[4] is the MSB.
a local processor.
Processor Address Bus. Used to select the internal registers and memory
locations of the MT90226.
Processor Read/Not Write (Motorola Mode). This is an input signal. If low,
data is written from the processor to the MT90226. If high, data is read from
the MT90226 to the processor.
Processor Not Write (Intel Mode). This is an input signal, active low. If low,
data is written from the processor to the MT90226.
Output enable (Motorola Mode). This is an input signal. This signal should
be tied to GND for Motorola timing mode.
Processor Read (Intel Mode). This is an input signal, active low. If low, data is
read from the MT90226.
Chip Select. This is an active low input signal. If this signal is high, the
MT90226 ignores all other signals on its processor bus. If this signal is low, the
MT90226 accepts the signals on its processor bus.
MT90226 signals to the processor that an interrupt condition is pending inside
the MT90226.
output is set to high impedance for unused time slots and if the link is not used.
It is aligned with TXCKio and TxSYNCio.
Processor Interface Signals
TDM Interface Signals
Zarlink Semiconductor Inc.
Description
Data Sheet