mt90226ag ETC-unknow, mt90226ag Datasheet - Page 52

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

52
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Bin):
15:12
Bit #
Bit #
Bit #
11:0
11:8
15:8
7:4
3:0
4:1
13
12
7
6
5
0
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
Unused. Read all 0’s.
Status Bit. Goes to 0 during initialization and returns to 1 on completion of initialization.
Write 1 to this bit for normal operation. Write 0 in conjunction with bit 0 to initialize the TX
Cell RAM;
Reserved. Write 0 for normal operation.
Reserved. Write 0’s for normal operation.
Write 0 to initialize the internal Cell RAM.
Reading a 1 in this register indicates that the transfer to bits 11:0 has completed. Reading
a 0 indicates that the transfer is not completed yet.
When this bit is set the TX UTOPIA Parity Error Counter will be reset. When this bit is
reset the TX UTOPIA Parity Error Counter will operate normally.
TX UTOPIA Parity Error Counter. These bits contain the value of the TX UTOPIA Parity
Error Counter. The counter must be loaded into the register using bit 13.
Unused. Read 0’s.
TX UTOPIA FIFO Length for Link N+8.
Reserved. Write 0’s for normal operation.
TX UTOPIA FIFO Length for Link N.
Table 12 - TX Link UTOPIA FIFO Length Definition Register
Table 10 - UTOPIA Input Parity Error Register (continued)
1 register per 2 links. Link 0 is paired with link 8, link 1 is paired with link 9 and so
0x0053 (1 reg)
1 register to contain information about parity errors on the Tx UTOPIA data bus.
0000
0x008B-0x0092 (8 reg)
0101
on.
0x0080 (1 reg)
Used for initialization of the internal TX Internal Cell RAM (Idle Cell)
000000001X000000
Table 11 - TX Cell RAM Control Register
Zarlink Semiconductor Inc.
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