mt90226ag ETC-unknow, mt90226ag Datasheet - Page 44

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

44
The IRQ enable bit of a counter is set, or reset, by selecting the counter and writing to the appropriate bit of the
Counter Transfer Command (0x040F) register. The value’0x001010’ enables the counter IRQ and ’xxx00010’
disables (masks) it.
6.1.5
An additional mode of operation is available in the counter block where the values of all the counters are transferred,
all at the same time, to a series of internal registers. The transfer can be initiated automatically based on an input
signal or following a transfer command under software control.
When the source for the latch command is from the dedicated input pin, the user has the option to use directly this
signal as a latch command or to divide the incoming signal by 8000 before generating the latch command (for
example, using the 8 kHz F0 frame pulse signal to create 1 second intervals). Bits in the Counter Transfer
Command (0x040F) register are defined to support these features.
The counters are 24 bits wide when operated without the latching option and are 16 bits wide when the latching
feature is enabled. After each latch signal, the counters are reset to 0 in order to report the number of events
between two latch commands.
Before the latching mode is enabled, the counters may be loaded (or reset), but the software should not write to the
counters after the latching mode is enabled.
6.2
The MT90225/226 can generate interrupts from many sources. All interrupt sources can be enabled or disabled.
Write action is required to clear the source of interrupt. Interrupts are grouped on a per link basis, with six
sub-categories for each link. These special interrupts are only present in the Link 0 IRQ Status register. Refer to
Figure 14 for a representation of the interrupt register hierarchy.
Latching counter mode
Interrupt Block
RX FIFO Overflow
4 UTOPIA
1 UTOPIA
Counters
Counters
Counters
Link Overflow Status
3 RX
2 TX
Figure 14 - IRQ Register Hierarchy
Link 15
End of LCD
Link 14
S
T
A
T
U
S
Zarlink Semiconductor Inc.
Link 13
.......
LCD
Link 3
Registers
16 x IRQ
Link 2
Link
1
9
0
Link 1
S
T
A
T
U
S
Link 0
N
E
A
B
L
E
Link 15
Link 0
Registers
1 x IRQ
Master
S
T
A
T
U
S
N
E
A
B
L
E
Data Sheet
IRQ PIN