mt90226ag ETC-unknow, mt90226ag Datasheet - Page 19

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
MT90225 Pin Description (continued)
V25,W26,W23,
P26,M26,M24,
U24,V23,W24,
H25,G26,G24,
H23,G25,F25,
N26,M25,L26,
H24,G23,F23,
D26,D25,B24,
C22,C21,A21,
P25,N24,M23,
E26,C26,A25,
B23,A22,B21,
R25,T25,U26,
A24,B22,D21,
R26,T26,T24,
F24,E24,C23,
L24,K24,J23,
K26,J26,J24,
L25,K25,J25,
AB25,AC25,
AB24,AD26,
AC21,AD20,
AD19,AD18,
AE22,AF21,
AF20,AF19,
AE18,AF17
AF18,AD16
Y25,AA26,
Y24,AA24,
AA3,AA4,
AB2,AB1
AA1,Y3
Pin #
AC1
C20
B20
A20
TXSYNCio
RXSYNCi
PLLREF
TXCKio
REFCK
RXCKi
Name
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
DSTi
[1:0]
[3:0]
Clk
I/O
I/O TDM Interface Transmit Clock 15-0. This pin is an input or an output as
I/O Transmit Line Frame Pulse 15-0. This pin is an input or an output as
O Output reference to an external PLL.
I
I
I
I
I
Serial TDM Data Input 15-0. Serial stream which contains receive data. It is
aligned with RXCKi and RXSYNCi. These pins have internal weak pull-downs.
selected by the TDM TX Link Control registers. The TXCK source is software
selectable and can be either one of the sixteen RXCK or one of the four
REFCK signals when defined as output. When defined as input, the proper
clock signal is provided to the input pin. The clock polarity is determined by the
TDM TX Link Control registers. These pins have internal weak pull-downs.
selected by the TDM TX Link Control registers.
It is the frame reference (typically 8 kHz) used as transmit synchronization for
the TDM system interface. When an output, the TXSYNC is generated from
the TXCK signal and is independent from other TXSYNC signals. Two major
modes are available: generic and ST-BUS:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the
32/64/128 channel frame of the ST-BUS interface at DSTo lines.
2. For generic TDM Interfaces, it can be programmed to generate or receive
either a positive or negative pulse polarity that marks the first bit of the TDM
system interface. These pins have internal weak pull-downs.
Receive line Frame Pulse 15-0. It is the frame reference (typically 8 kHz)
used as receive synchronization for the TDM system interface. Two major
modes are available: generic and ST-BUS:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the
32/64/128 channel frame of the ST-BUS interface at DSTi lines.
2. For generic TDM Interfaces, it can be programmed to accept either a
positive or negative pulse polarity that marks the first bit of the TDM system
interface. These pins have internal weak pull-downs.
TDM Interface Receive Clock 15-0. This input line represents the clock for
the receive serial TDM data. The expected frequency value to be received at
this input clock is defined by the user through the RX Link TDM Control
register. These pins have internal weak pull-downs.
Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock
reference to be internally routed to the TXCKio transmit clocks. These pins
have internal weak pull-downs.
System Clock (50 MHz nominal). In the MT90225, this clock is used for all
internal operations of the device.
Zarlink Semiconductor Inc.
System Signals
Description
19