mt90226ag ETC-unknow, mt90226ag Datasheet - Page 39

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
5.0
The MT90225/226 supports the UTOPIA L1 and L2 Mode, 8 or 16 bit wide bus at up to 52MHz, with odd/even parity,
for cell level handshake only. Each port can be assigned an address ranging from 0 to 30. The address value of 31
is reserved and should not be used.
The TX and RX paths of each link has its own PHY address. These PHY addresses are defined in the UTOPIA
Input Link Address (0x0040-0x0047) and UTOPIA Output Link Address (0x000-0x0007) registers. The UTOPIA
Input LINK PHY Enable (0x0050) and the UTOPIA Output Link PHY Enable (0x0010) registers are used to
enable the PHY address of the links.
The MT90225/226 UTOPIA port uses handshaking signals to process data streams. The start of a cell (SOC) is
marked by the UTOPIA SOC sync signal. This signal is active during the transfer of the first byte of a cell. The 52
bytes that follow the arrival of the first byte of a cell are interpreted as belonging to the same cell and are stored
accordingly (note that SOC sync signals received during the loading of these 52 bytes are ignored).
The Cell Available status line (Clav) is used to communicate to the ATM controller whether the MT90225/226 has
space for a cell in the PHY address that was polled in the previous cycle. Whenever there is space for a cell in the
TX direction or a cell ready in the RX direction, the TXClav and/or RXClav signal will be driven High or Low. When
the address does not correspond to any enabled PHY address inside the MT90225/226, the TXClav and RXClav
signal are set to high impedance mode. The use of an external pull-down may be required for the proper operation
of the Utopia bus in MPHY mode.
Note that the transmit or receive Utopia clock frequencies do not have to be synchronized with the system clock by
their frequencies cannot exceed the system clock frequency.
5.1
The UTOPIA interface input clock TxClk is independent of the system clock. The UTOPIA TxClk can be up to 52
MHz. The incoming cell is stored directly in the internal TX Cell RAM where the TX UTOPIA FIFOs are implemented.
The Tx byte clock (TxClk) is checked against the system clock. If the incoming byte clock frequency is lower than
1/128 of the system clock, bit 2 of the General Status (0x040E) register will be set. This bit is cleared by overwriting
it with 0. This aids in debugging as the presence of a UTOPIA clock is required not only for data transfer but also
for proper operation of the UTOPIA registers.
The total space for the UTOPIA input cells for all links is 118. These 118 cells are shared between 16 TX UTOPIA
FIFOs. The size (length) of each TX UTOPIA FIFO is defined by writing to the TX LINK FIFO Length Definition
(0x008B-0x0092) registers.
The device will not accept a cell from the UTOPIA Interface if the internal Cell Ram is full. Status bit 0 in the General
Status (0x040E) register is set to 1 to indicate the ’no free cell in TX Cell RAM’ condition. The status bit can be
cleared by overwriting it with 0.
The UTOPIA Input block has the option to verify the HEC of the cell coming from the ATM layer. Four different
options are available and are selected by bits 1 and 0 of the UTOPIA Input Control (0x0052) register.
•
•
The ’00’ option is used to always accept a cell from the ATM layer. The HEC is verified and if wrong, the
UTOPIA Input counter associated with the UTOPIA port for cells with bad HEC is incremented. The
MT90225/226 will re-generate a valid HEC based on the content of the 4-byte header that was received.
The ’01’ option is used to verify the HEC of an incoming cell. If the HEC value is wrong and if it can be
corrected (1 bit error), then the cell is corrected and accepted as a good cell. The bad HEC counter is not
incremented if the HEC is corrected. The bad HEC counter is incremented if the HEC value cannot be
corrected. In this mode, the cell is always accepted. The MT90225/226 will re-generate a valid HEC based
on the content of the 4-byte header that was received.
UTOPIA Interface Operation
ATM Input Port
Zarlink Semiconductor Inc.
39