mt90226ag ETC-unknow, mt90226ag Datasheet - Page 29

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
4.0
The Transmit TDM blocks are independent of the Receive TDM blocks. The TX port of a framer can be connected
to any of the MT90225/226 TX UTOPIA Input ports and the RX port of a framer can be connected to any of the
MT90225/226 RX UTOPIA Output ports.
The TDM interface provides a variety of modes to work with different T1/E1/DSL framers for various applications.
In general, there are four major modes: Single mode, Wire-OR mode, Multiplex mode and Non-framed mode. Each
mode can be further divided into several minor modes.
4.1
In this mode, all links are active and can be used. Its minor modes of operation include Generic 1.544MHz mode
(F-bit and 24 time slots), Generic 2.048MHz mode (32 time slots), and ST-BUS mode (32 time slots).
Mapping registers are used to determine when a time slot is used to carry the ATM traffic. There are two 16-bit
mapping registers for each TDM TX and for each TDM RX links. Each bit of the 2 registers (total of 32 bits) controls
one time slot. A bit value of 1 corresponds to an active time slot. A value of 0 corresponds to an inactive time slot
and the output is in High Impedance mode for that time slot. The TDM TX link is independent of the TDM RX link
and can have different mapping (using different time slots and optionally a different number of time slots).
Fractional T1/E1 and nx64 channel modes are implemented by programming bits in the mapping registers to enable
the use of the required time slots.
4.1.1
This is also known as T1 generic mode. In this mode, data rate is 1.544 Mb/s, clock is 1.544 MHz and frame pulse
is 8 KHz. A frame is 193 bits long and a frame pulse is present (either generated or accepted as input). The first bit,
indicated by the frame pulse, is not used to carry any useful information; it is in high impedance on Tx link and is
ignored on Rx link. The 24 time slots (192 bits) are controlled by the lowest 24 bits of the mapping register
associated with a link. Fractional T1 is supported by activating (selecting) any of the first 24 time slots defined in the
mapping register.
Note: Both frame pulse polarity and clock edge are programmable.
Description of the TDM Interface
Single mode
Single mode - Generic 1.544MHz
T1 Frame
Bit Cells
at DSTx0-15
Serial Bit
Stream
TXSYNC
TXCK
RXSYNC
RXCK
Figure 8 - Single mode - Generic 1.544 MHz
Bit Cell
bit 193
Zarlink Semiconductor Inc.
High Impedance
Unused or
bit 1
Bit Cell
bit 2
...
...
...
...
...
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