mt90226ag ETC-unknow, mt90226ag Datasheet - Page 60

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mt90226ag

Manufacturer Part Number
mt90226ag
Description
16/8 Port Tc Phy Device
Manufacturer
ETC-unknow
Datasheet
60
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
15:12
15:0
Bit #
10
11
9
8
7
6
5
4
3
2
1
0
Type
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
When set to 1, any bit set in the IRQ Link TC Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. Each bit corresponds to 1 link.
Unused. Read all 0’s.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
A ’1’ indicates the end of the LCD condition. Cleared by writing a ’0’.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
LCD Loss of Cell Delineation. This status bit can be cleared by writing a ’0’ to it.
Link Counter Overflow Interrupt. One or more counters associated with the link
overflowed. This status bit can be cleared only by reading or writing to the counter(s)
which is (are) the source for the IRQ.
0x0434 (1 reg)
1 register to enable interrupts from the links in TC mode. The RxClk signal must
be active for correct register operation
00
0x0435 - 0x0444 (16 reg)
1 Status register per link
0000
Table 29 - IRQ Link TC Overflow Enable Register
Table 30 - IRQ Link Status Registers
Zarlink Semiconductor Inc.
Description
Description
Data Sheet

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