mt90226ag ETC-unknow, mt90226ag Datasheet - Page 45

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
6.2.1
There is a IRQ Master Status (0x0455) register that reports interrupts generated by any event on any of the links.
Each bit of this register corresponds to a link. A ’1’ in a bit position indicates that the associated link is reporting an
interrupt condition. For each bit in the IRQ Master Status (0x0455) register, there is a corresponding bit in the IRQ
Master Enable (0x0433) register. When any IRQ source is active and the corresponding Enable bit is ’1’, then the
IRQ pin will go LOW (active).
The IRQ Master Status (0x0455) register always reports the current state of the source(s) of interrupt. It does not
latch the interrupt request(s); it only reports that one or more bit(s) in one or more IRQ Link Status register(s) is
(are) set.
The bits that are read as active (’1’ value) are cleared when the source of the interrupt is cleared or when the
corresponding bit(s) in the IRQ Link Enable (0x0445-0x0454) register(s) is (are) set to 0. Writing to or reading from
the IRQ Master Status (0x0455) register has no effect on the level of the interrupt pin.
6.2.2
There are sixteen IRQ Link Status (0x0435-0x0444) and sixteen IRQ Link Enable (0x0445-0x0454) registers; one
of each per link. The following types of interrupts are reported (in the least significant bits of the IRQ Link Status
registers) for each link:
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Bit 0 (LSB) is a status bit. It reports an interrupt for an overflow condition in one or more of the 24 counters
associated with the link. It is also used to report an overflow condition in the UTOPIA RX FIFO associated with a
TDM link in TC mode. If enabled, a counter generates an interrupt request when it overflows (i.e starts over from 0
after reaching the maximum counter value). See Section 6.1 Counter Block for more details on the operation of the
counters. These 13 sources of overflow can be identified through the IRQ Link FIFO Overflow and IRQ UTOPIA
FIFO Overflow status registers.
Reading the IRQ Link Status (0x0435-0x0444) register does not clear the source of interrupt. The bit 0 status is
reset by any one of the following procedures:
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Bits 1 to 6 and 9 to 11 of the IRQ Link Status (0x0435-0x0444) registers are latches that report the source of an
interrupt. Writing a ’0’ these bits will reset the status bit (will reset the latch). Writing ’0’ to bit 0 has no effect on the
status bit.
Writing a ’1’ has no effect on the bits 0 to 6 and 9 to 11 of the IRQ Link Status (0x0435-0x0444) register.
Each one of these 10 interrupt sources can be enabled by writing a ’1’ in the IRQ Link Enable (0x0445-0x0454)
registers to the bit corresponding to the interrupt source.
In some situations, an interrupt source can be masked as part of an interrupt service routine. This makes it possible
to detect further interrupts of higher priority. For example, if an interrupt for a counter is received, the source of the
interrupt can be masked by writing 0 to the corresponding bit and then starting a separate process outside of the
Interrupt Service Routine. The independent process would read, reload and re-enable the counter to produce
another interrupt service request, if necessary. At the end of this process, the enable bit in the IRQ Link Enable
(0x0445-0x0454) register would be set to ’1’ to detect any future interrupt requests.
Bit 9 latched: reports the end of an LCD (Loss of Cell Delineation) condition on a RX TDM link.
Bit 1 latched: reports an LCD (Loss of Cell Delineation) condition on a RX TDM link.
disabling (masking) the IRQ for this specific counter
clearing the overflow status bit in the IRQ Link TC Overflow Status (0x0410-0x041F) registers
disabling the interrupt in the IRQ Link TC Overflow Enable (0x0434) or in the corresponding Link Counter
registers.
IRQ Master Status and IRQ Master Enable Registers
IRQ Link Status and IRQ Link Enable Registers
Zarlink Semiconductor Inc.
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