mt90226ag ETC-unknow, mt90226ag Datasheet - Page 38

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

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4.8.2
The TXSYNC signal is used to align the outgoing DSTo data to retrieve all the T1 or E1 channels. When defined as
input, the TXSYNC pulse can be present for each TDM frame (8Khz) or once per Superframe (every 12 or 24 TDM
frames). The period and position of the TXSYNC is verified for each transmit block independently. A status bit (1 per
link) in the TXSYNC Status (0x0633) register is set if the synchronization pulse occurs at an unexpected time in the
frame. The TX block will be re-aligned with this new synchronization pulse.
4.8.3
Two output pins are provided to simplify the external circuitry required when using an external PLL. These two pins,
PLLREF0 and PLLREF1, re-route any of the RXCK signals and drive the primary and secondary reference signals
of a PLL under software control. Refer to Section 8, Application Notes, for examples.
4.8.4
The MT90225/226 implements circuitry to determine whether or not a selected clock signal is active. This feature is
used to ensure a clock is operational before using it as a source for one or more transmit links. A read of the TXCK
Status (0x0630), RXCK Status (0x0631) or REFCK Status (0x0632) register indicates a faulty clock if a bit is ’1’.
A value of ’0’ for these bits means that activity was observed on this clock. This circuitry does not measure the
frequency of a clock signal, it only detects activity on the TXCK, RXCK and REFCK signals.
4.8.5
The clock selection circuitry selects the desired clock signal and ensures a smooth, glitch free, transition between
the current clock source and the new clock source. Clock source activity can be verified using the TXCK Status
(0x0630), RXCK Status (0x0631) or REFCK Status (0x0632) registers.
Verification of the TXSYNC Period
Primary and Secondary Reference Signals
Verification of Clock Activity
Clock Selection
Zarlink Semiconductor Inc.
Data Sheet