mt90226ag ETC-unknow, mt90226ag Datasheet - Page 34

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

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4.4
Single mode, Wire-OR mode and Multiplexed mode are all dealing with framed data, that is, a frame pulse must be
present to give both byte and frame alignment. However, MT90225/226 also support a non-framed mode where only
a serial bit stream and clock are available for each link. Moreover, a wide range of data rate is supported by this
mode, which makes it particularly useful in DSL applications where the line rate may vary.
When used in Non-framed mode, RXSYNC must be de-asserted. For example, if RXSYNC is defined as active low
frame pulse (bit 0 cleared in TDM RX Link Control register), RXSYNC input pin must be tied to high. The same
applies to TXSYNC when it is an input pin.
Mapping registers must all be set to 0xFFFF in Non-framed mode. Serial clock rate and data rate must be the same.
Moreover, bit mode cell delineation (bit 10 in TDM RX Link Control registers) must be selected, and register 0x0741
must be written by 0x36.
Three minor modes are available in Non-framed mode, resulting to different data rate and link number.
4.4.1
In Non-framed mode, all links are able to run from 0 up to 2.5 Mb/s. On the transmit side, if the TXCK and TCSYNC
are programmed as inputs, TXSYNC must be disabled state, and the transmitter will be "free running" and will output
serial data continuously. If the TXSYNC is defined as output, a frame pulse is generated for every 256 TXCK cycles,
but can be ignored.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings.
4.4.2
If a serial link of more than 2.5Mbps but less than 5.0Mbps data rate is required, this mode can be applied. For every
two links in a pair, one is disabled and the other is able to run from 0 up to 5.0 Mb/s. The links that are paired are
pre-determined: link 0 with link 1, link 2 with link 3 and so on. The link that will remain enabled in each pair is also
pre-determined. They are link 0, 2, 4, 6, 8, 10, 12 and 14.
For the pair of link 0 and link 1, the pins associated with link 1 cannot be used and are tri-stated. On the transmit
side of link 0, if the TXCK and TCSYNC are programmed as inputs, TXSYNC must be de-asserted, and the
transmitter will be "free running" and will output serial data continuously. If the TXSYNC is defined as output, a frame
pulse is generated for every 512 TXCK cycles, but can be ignored. The same logic applies for the other pairs.
For any disabled link, its associated registers are all disabled, except for mapping registers that must be set to all
one. No other configuration is necessary for disabled links.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
writing the following settings into those enabled links only.
Data rate (bits 6:5) = 01
Multiplex mode (bits 4:3) = 00
Clock and Sync format (bit 2) = 0
Cell delineation mode (bit 10 of TDM RX Link Control only) = 1
Data rate (bits 6:5) = 10
Multiplex mode (bits 4:3) = 00
Clock and Sync format (bit 2) = 0
Cell delineation mode (bit 10 of TDM RX Link Control only) = 1
Non-framed mode
Non-framed mode - 2.5Mbps
Non-framed mode - 5.0Mbps
Zarlink Semiconductor Inc.
Data Sheet