mt90226ag ETC-unknow, mt90226ag Datasheet - Page 7

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

MT90225/226
Data Sheet
List of Tables
Table 1 - Cell Acquisition Time..............................................................................................................................27
Table 2 - Register Summary .................................................................................................................................47
Table 3 - UTOPIA Output Link Address Registers ................................................................................................48
Table 4 - UTOPIA Output Link PHY Enable Registers..........................................................................................48
Table 5 - UTOPIA Output Control Register ...........................................................................................................49
Table 6 - UTOPIA Output User Defined Byte ........................................................................................................49
Table 7 - UTOPIA Input Link Address Registers ...................................................................................................49
Table 8 - Utopia Input Link PHY Enable Registers ...............................................................................................50
Table 9 - UTOPIA Input Control Register ..............................................................................................................51
Table 10 - UTOPIA Input Parity Error Register .....................................................................................................51
Table 11 - TX Cell RAM Control Register .............................................................................................................52
Table 12 - TX Link UTOPIA FIFO Length Definition Register ...............................................................................52
Table 13 - RX Link Control Registers....................................................................................................................53
Table 14 - Loss of Delineation Register ................................................................................................................53
Table 15 - Cell Delineation Register......................................................................................................................54
Table 16 - RX Link Select Register .......................................................................................................................54
Table 17 - RX State Register ................................................................................................................................54
Table 18 - Cell Delineation Status Register ..........................................................................................................55
Table 19 - Reset Register .....................................................................................................................................55
Table 20 - TX Link Control Registers ....................................................................................................................56
Table 21 - UTOPIA Input Cell Counter Register ...................................................................................................56
Table 22 - General Status Register .......................................................................................................................57
Table 23 - Counter Transfer Command Register ..................................................................................................57
Table 24 - IRQ Link Overflow Status Registers.....................................................................................................58
Table 25 - Counter Byte 3 Register .......................................................................................................................58
Table 26 - Counter Bytes 2 and 1 Register ...........................................................................................................59
Table 27 - Select Counter Register .......................................................................................................................59
Table 28 - IRQ Master Enable Register ................................................................................................................59
Table 29 - IRQ Link TC Overflow Enable Register................................................................................................60
Table 30 - IRQ Link Status Registers....................................................................................................................60
Table 31 - IRQ Link Enable Registers...................................................................................................................61
Table 32 - IRQ Master Status Register .................................................................................................................61
Table 33 - TDM TX Link Control Register .............................................................................................................61
Table 34 - TDM TX Mapping (timeslots 15:0) Register .........................................................................................62
Table 35 - TDM TX Mapping (timeslots 31:16) Register .......................................................................................63
Table 36 - TXCK Status Register ..........................................................................................................................63
Table 37 - RXCK Status Register..........................................................................................................................63
Table 38 - REFCK Status Register .......................................................................................................................64
Table 39 - TXSYNC Status Register .....................................................................................................................64
Table 40 - PLL Reference Control Register ..........................................................................................................64
Table 41 - TDM RX Link Control Register.............................................................................................................65
Table 42 - TDM RX Mapping (timeslots 15:0) Register.........................................................................................66
Table 43 - TDM RX Mapping (timeslots 31:16) Register.......................................................................................66
Table 44 - RXSYNC Status Register.....................................................................................................................66
Table 45 - RX Automatic ATM Synchronization Register......................................................................................66
Zarlink Semiconductor Inc.
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