mt90226ag ETC-unknow, mt90226ag Datasheet - Page 48

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

48
7.2
Address (Hex):
Direct access
Reset Value (Hex):
0x0600 - 0x060F
0x0610 - 0x061F
0x0620 - 0x062F
0x0700 - 0x070F
0x0710 - 0x071F
0x0720 - 0x072F
Address (Hex):
Direct access
Reset Value (Hex):
0x0634- 0x0635
15:13
Bit #
Bit #
12:8
7:5
4:0
15
14
...
1
0
Address
0x0630
0x0631
0x0632
0x0633
0x0730
0x0741
(Hex)
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
Detailed Register Description:
...
R
R
Access
Enable UTOPIA PHY address of link 15. A 1 enables the PHY port address.
Enable UTOPIA PHY address of link 14. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of link 1. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of link 0. A 1 enables the PHY port Address.
...
Unused. Read all 0’s.
UTOPIA PHY Address of link N+8.
Unused. Read all 0’s.
UTOPIA PHY Address of link N.
Type
0x0010 (1 reg)
1 register to for all links.
0000
D
D
D
D
D
D
D
D
D
D
D
D
D
0x000-0x007 (8 regs)
1 register per 2 links. Link 0 is paired with link 8, link 1 with link 9 and so on.
0000
Table 4 - UTOPIA Output Link PHY Enable Registers
Table 3 - UTOPIA Output Link Address Registers
Table 2 - Register Summary (continued)
Reset Value
(Hex)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Zarlink Semiconductor Inc.
TDM TX Link Control Register
TDM TX Mapping (timeslots 15:0) Register
TDM TX Mapping (timeslots 31:16) Register
TXCK Status Register
RXCK Status Register
REFCK Status Register
TXSYNC Status Register
PLL Reference Control Register
TDM RX Link Control Register
TDM RX Mapping (timeslots 15:0) Register
TDM RX Mapping (timeslots 31:16) Register
RXSYNC Status Register
RX Automatic ATM Synchronization Register
Description
Description
Description
Data Sheet