mt90226ag ETC-unknow, mt90226ag Datasheet - Page 18

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

18
MT90225 Pin Description (continued)
AE7,AD7,AC7,
AE8,AD8,AF7,
AF5,AE5,AD5,
AE4,AF3,AD4,
U25,V24,W25,
L1, L2, L4, L3,
P24,R23,T23,
AE12,AC12,
AB26,AC26,
AC24,AE21,
AC11,AD11,
AF10,AE10,
AE20,AE19,
AF11,AE11,
AC18,AD17
AD10,AF9,
AF6,AD6,
AE9,AD9
Y26,Y23,
AE3,AF2
AD13
Pin #
AF12
AE13
AC9
K1
J3
URxAddr
URxClav
up_r/w
Name
up_wr
up_oe
up_irq
up_cs
[15:0]
up_rd
[15:0]
[11:0]
DSTo
up_d
up_a
[4:0]
or
or
I/O
I/O Processor Data Bus. Data Bus to exchange data between the MT90225 and
O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY
O Processor Interrupt Request. Open drain signal. If this signal is low, the
O Serial TDM Data Output 15-0. Serial stream which contains transmit data.
I
I
I
I
I
environment, URxClav is an active high tri-stateable signal from the MT90225
to ATM LAYER device.
Receive Address. Five bit wide address bus driven from the ATM to PHY
device to select the appropriate PHY address. URxAddr[4] is the MSB.
a local processor.
Processor Address Bus. Used to select the internal registers and memory
locations of the MT90225.
Processor Read/Not Write. Motorola Mode. This is an input signal. If low,
data is written from the processor to the MT90225. If high, data is read from
the MT90225 to the processor.
Processor Not Write (Intel Mode). This is an input signal, active low. If low,
data is written from the processor to the MT90225.
Output enable (Motorola Mode). This is an input signal. This signal should
be tied to GND for Motorola timing mode.
Processor Read (Intel Mode). This is an input signal, active low. If low, data
is read from the MT90225.
Chip Select. This is an active low input signal. If this signal is high, the
MT90225 ignores all other signals on its processor bus. If this signal is low, the
MT90225 accepts the signals on its processor bus.
MT90225 signals to the processor that an interrupt condition is pending inside
the MT90225.
The output is set to high impedance for unused time slots and if the link is not
used. It is aligned with TXCKio and TXSYNCio.
Processor Interface Signals
TDM Interface Signals
Zarlink Semiconductor Inc.
Description
Data Sheet