mt90226ag ETC-unknow, mt90226ag Datasheet - Page 37

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
4.8
TXCK and TXSYNC can be either input or output signals. When TXCK and TXSYNC are inputs, they are generated
by external circuitry. When TXCK and TXSYNC are outputs, TXCK source is software selectable and can be any of
the RXCK signals or four external REFCK inputs (see Figure 11). The TXSYNC is generated from the TXCK signal.
The RXCK pins are always defined as inputs and the proper signal must be provided to each input.
4.8.1
The RXSYNC signal is used to align the incoming DSTi data to retrieve all the T1 or E1 channels. The RXSYNC
pulse can be present for each TDM frame (8Khz) or once per Superframe (an integer number of frames, typically
12 or 16). The period and position of the RXSYNC is verified for each receive block independently. A status bit (1
per link) in the RXSYNC Status (0x0730) register is set if the synchronization pulse occurs at an unexpected time
in the frame. The RX block will be re-aligned with this new synchronization pulse.
Clocking Options
Verification of the RXSYNC Period
Figure 11 - TXCK and TXSYNC Output Pin Source Options
RXCK 0-15
REFCK 0-3
RXCK 0-15
TX Cell FIFO
Cell Delineation
Zarlink Semiconductor Inc.
P/S
S/P
PLLREF1
PLLREF0
DSTi
RXCK
RXSYNC
TXSYNC
DSTo
TXCK
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