mt90226ag ETC-unknow, mt90226ag Datasheet - Page 27

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
When a valid HEC is found, the CD circuit locks on the cell boundary and enters the PRESYNC state. The
PRESYNC state keeps checking the HEC to ensure that the previous indication was not false. False indications are
interpreted to mean the circuit is not tracking valid ATM cells. After entering the PRESYNC state, the first false
indication triggers a transition back to HUNT state.
If the PRESYNC state HEC is correct, then a transition to the SYNC state occurs after “ ” cells (DELTA in ITU I.432)
are correctly received. In the SYNC state, the CD circuit treats the incoming ATM cell stream as stable and the
MT90225/226 functions normally.
While in the SYNC state, if an incorrect HEC is obtained “ ” consecutive times (ALPHA in ITU I.432), cell delineation
is considered lost and a transition is made back to the HUNT state (see Figure 5).
As defined by the ITU I.432 recommendations, the value of ALPHA and DELTA determine the robustness of the
delineation method. The value of ALPHA and DELTA for the Cell Delineation state machine are defined in the Cell
Delineation (0x00C9) register. Only one set of values is defined for the sixteen Cell Delineation state machines.
The status of the CD state machine for each link is available in bits 0 through 15 of the Cell Delineation Status
(0x00E6) register.
The ITU I.432 suggested values are: ALPHA = 7; and DELTA = 6.
Loss of Cell Delineation (LCD) is detected by counting the number of incorrect cells while in HUNT state. The
MT90225/226 provides an internal Loss of Delineation (0x00C8) register to set the threshold for this count. A value
of 360 in the LCD register would correspond to 79 msec for E1 and 100 msec for T1 applications. The LCD state
for each link is available in bit 1 of the IRQ Link Status (0x0435 - 0x4444) registers.
The LCD and End of LCD status bit reports the current condition of the Cell Delineation State Machine at the time
it is read, and can optionally generate an interrupt (IRQ). Table 1 provides the time, in microseconds, for the CD
circuit to receive a full ATM cell from the T1 and E1 frame payloads.
While the cell delineation state machine is in the SYNC state, the verification circuit implements the state machine
shown in Figure 7.
In normal operation, the HEC verification state machine remains in the’correction’ state. Incoming cells containing
no HEC errors are passed through. Incoming single-bit errors can be corrected if required by the application (i.e.,
single bit error correction can be enabled or disabled).
(PRESYNC State)
Correct HCS’s
Consecutive
DELTA
Accepted
Cell
Correction
Format
E1
T1
HCS Single Bit Error Detected (corrected or dropped)
ATM CELL DELINEATION SYNC STATE
Figure 7 - SYNC State Block Diagram
Table 1 - Cell Acquisition Time
HCS Multi-Bit Error Detected (cell discarded)
Zarlink Semiconductor Inc.
No HCS Errors Detected
Average Cell Time ( s)
276
221
Detection
Discarded
Cell
Incorrect HCS’s
Jump to HUNT
Consecutive
ALPHA
State
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