mt90226ag ETC-unknow, mt90226ag Datasheet - Page 31

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
4.1.3
This is used for T1/E1 connection with ST-BUS, where data rate is 2.048 Mb/s, clock is 4.096 MHz and frame pulse
is 8KHz. A standard ST-BUS mode is supported with 32 time slots in each frame. The Frame format and clock speed
meet the ST-BUS or MVIP standard. The mapping registers are used to determine which of the 32 time slots are
used to carry TDM traffic.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings.
4.2
In this mode, two or four links are logically OR’ed together to share a single stream. This is particularly useful for
fractional T1/E1 applications where links using different time slots can be multiplexed together onto a single stream
in order to facilitate the interface to a single T1 or E1 framer.
Links that are OR’ed together can have any one of the Single mode discussed in Section 4.1. To avoid any
contention, mapping registers of those links must not have the same bit set.
All links in Wire-OR mode must be configured in the same as they were in Single mode, except for TDM Link
Control registers. Two minor modes are available, 2-link grouping and 4-link grouping.
Note: Frame pulse polarity and clock edge are fixed in ST-BUS mode.
Data rate (bits 6:5) = 01
Multiplex mode (bits 4:3) = 00
Clock and Sync format (bit 2) = 1
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
ST-BUS
Bit Cells
(DSTx0-15)
Serial Bit
Stream
TXSYNC
RXSYNC
TXCK
RXCK
Single mode -ST-BUS
Wire-OR mode
Channel 31 bit 0
Bit Cell
Figure 10 - Single mode - ST-BUS
Channel 0 bit 7
Zarlink Semiconductor Inc.
Bit Cell
...
...
...
...
Channel 0 bit 0
Bit Cell
Channel 1 bit 7
Bit Cell
...
...
...
...
31