mt90226ag ETC-unknow, mt90226ag Datasheet - Page 30
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mt90226ag
Manufacturer Part Number
mt90226ag
Description
16/8 Port Tc Phy Device
Manufacturer
ETC-unknow
Datasheet
1.MT90226AG.pdf
(91 pages)
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30
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings.
4.1.2
This is used for generic nx64 connections, where n can be any number from 1 to 32. In this mode, data rate is 2.048
Mb/s. A clock of 2.048 MHz is used and the Frame pulse is indicating the first bit of the first time slot of a frame of
32 time slots. The mapping registers are used to determine the number of time slots used and their position in the
frame. This enables a direct interface to existing T1 or E1 framers and opens up the option to interface to generic
nx64 devices. Fractional T1/E1 is supported as well by selecting the time slots that are used to carry ATM traffic.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings.
Note: Both frame pulse polarity and clock edge are programmable.
Data rate (bits 6:5) = 00
Multiplex mode (bits 4:3) = 00
Clock and Sync format (bit 2) = 0
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
Data rate (bits 6:5) = 01
Multiplex mode (bits 4:3) = 00
Clock and Sync format (bit 2) = 0
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
RXSYNC
Serial Bit
Stream
TXCK
RXCK
ST-BUS
Bit Cells
(DSTx0-15)
TXSYNC
Single mode - Generic 2.048MHz
Channel 31 bit 0
Bit Cell
Figure 9 - Single mode - Generic 2.048 MHz
Channel 0 bit 7
Bit Cell
Zarlink Semiconductor Inc.
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Channel 0 bit 0
Bit Cell
Channel 1 bit 7
Bit Cell
Data Sheet
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