mt90226ag ETC-unknow, mt90226ag Datasheet - Page 61

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
14:10
Bit #
Bit #
Bit #
15:0
11:0
15
9
8
Type
Type
Type
R/W
R/W
R/W
R/W
R
R
R
Each bit represents a link. A ’1’ means that the corresponding link has a valid request for
interrupt. The level of the IRQ pin is controlled by the bits in this register and the
corresponding bits in the IRQ Master Enable Register. A write does not have any affect on
the bits in this register. The status bit is not latched and changing the mask bit in the IRQ
Master Register has a direct effect on the level of the IRQ pin.
Unused. Read all 0’s.
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ Link Status register is set.
Unused. Read 0.
Clock source select
These 4 bits are used to select the source for the TXCK for the link:
The valid combinations are:
00000: RXCK0
00010: RXCK2
00100: RXCK4
00110: RXCK6
01000: RXCK8
01010: RXCK10
01100: RXCK12
01110: RXCK14
10000: REFCK0
10010: REFCK2
Clock and sync direction
When 0, TXCK and TXSYNC are outputs.
When 1, TXCK and TXSYNC are inputs.
Remote Loopback
When 1, TXCK, TXSYNC and DSTo come from the RX pins of the same link.
When 0. normal mode.
0x0445 - 0x0454 (16 reg)
1 Enable register per link Status reg
0000
0x0455 (1 reg)
1 register for all 16 links
0000
0x0600 - 0x060F (16 reg)
1 reg. per TX link.
0000
Table 33 - TDM TX Link Control Register
Table 32 - IRQ Master Status Register
Table 31 - IRQ Link Enable Registers
Zarlink Semiconductor Inc.
01111: RXCK15
00111: RXCK7
01101: RXCK13
00001: RXCK1
00011: RXCK3
00101: RXCK5
01001: RXCK9
01011: RXCK11
10001: REFCK1
10011: REFCK3
Description
Description
Description
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